JPS5591835A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPS5591835A
JPS5591835A JP16397478A JP16397478A JPS5591835A JP S5591835 A JPS5591835 A JP S5591835A JP 16397478 A JP16397478 A JP 16397478A JP 16397478 A JP16397478 A JP 16397478A JP S5591835 A JPS5591835 A JP S5591835A
Authority
JP
Japan
Prior art keywords
substrate
top surface
onto
insulating layer
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16397478A
Other languages
Japanese (ja)
Inventor
Yoshiharu Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP16397478A priority Critical patent/JPS5591835A/en
Publication of JPS5591835A publication Critical patent/JPS5591835A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To prevent a substrate from being deformed by thermal variation and improve its reliability, by fixing an electronic part or a semiconductor chip onto the top surface of the substrate and securely attaching an insulating layer and a holding layer of the equal thermal expansion rate onto thus prepared top surface and also onto bottom surface thereof respectively.
CONSTITUTION: Surface of a semiconductor chip 12 formed on top surface of a metallic substrate 11 is provided with formation of an Au plated layer 13 with a thickness of 3μ, and difference in level between an insulating layer 14 of phenol resin on the top surface (or the substrate) and top surface 15 of the semiconductor chip 12 is kept within a range of 15μ. A holding layer 16, which is made of the same material and to almost the same width as the insulating layer 14, is attached onto the opposite surface of the substrate 11. A wiring pattern 19, formed by screen printing method, is arranged and securely attached onto the surface of the insulating layer 14 in such a manner as to contain an external take-out electrode 20 of the semiconductor chip 12. As the insulating layer and the holding layer are respectively arranged onto top surface and bottom surface of the substrate, it is possible to obtain the substrate of high reliability.
COPYRIGHT: (C)1980,JPO&Japio
JP16397478A 1978-12-29 1978-12-29 Electronic device Pending JPS5591835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16397478A JPS5591835A (en) 1978-12-29 1978-12-29 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16397478A JPS5591835A (en) 1978-12-29 1978-12-29 Electronic device

Publications (1)

Publication Number Publication Date
JPS5591835A true JPS5591835A (en) 1980-07-11

Family

ID=15784346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16397478A Pending JPS5591835A (en) 1978-12-29 1978-12-29 Electronic device

Country Status (1)

Country Link
JP (1) JPS5591835A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169266A (en) * 1981-04-09 1982-10-18 Sharp Corp Integrated circuit element
JPS6411357A (en) * 1987-07-04 1989-01-13 Horiba Ltd Method of taking out lead of semiconductor chip component
JPH09162346A (en) * 1995-12-08 1997-06-20 Kenseidou Kagaku Kogyo Kk Novel lead frame

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169266A (en) * 1981-04-09 1982-10-18 Sharp Corp Integrated circuit element
JPS6411357A (en) * 1987-07-04 1989-01-13 Horiba Ltd Method of taking out lead of semiconductor chip component
JPH09162346A (en) * 1995-12-08 1997-06-20 Kenseidou Kagaku Kogyo Kk Novel lead frame

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