JPS559205A - Pulse integration method - Google Patents

Pulse integration method

Info

Publication number
JPS559205A
JPS559205A JP7975778A JP7975778A JPS559205A JP S559205 A JPS559205 A JP S559205A JP 7975778 A JP7975778 A JP 7975778A JP 7975778 A JP7975778 A JP 7975778A JP S559205 A JPS559205 A JP S559205A
Authority
JP
Japan
Prior art keywords
computer
contact
integration
counter
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7975778A
Other languages
Japanese (ja)
Inventor
Shigeru Shirasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7975778A priority Critical patent/JPS559205A/en
Publication of JPS559205A publication Critical patent/JPS559205A/en
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Abstract

PURPOSE: To automatically obtain the integrating amount of pulse value including the value at computer halt, by automatically reading in and adding the integration value memorized in the readout counter by means of the electronic computer.
CONSTITUTION: At the same time when the function of the electronic computer 1 is stopped, the failuer signal such as power failure, stall, and parity error closes the contact 3 which is a component of the pulse signal output selector 2, to activate the relay 4 and to select the output of the pulse signal 5 from the computer 1 to the readout counter 7 with the selecting contact 6. Further, during the halt of computer 1, this counter 7 stores the integration amount, and when the computer 1 is restored, the contact 3 is open, the excitation of the relay 4 is deenergized, and the output of the signal 5 is selected to the computer 1 with the contact 6 again. Next, the computer 1 reads in the integration amount stored in the counter 7 and the integration amount memorized in the computer 1 is corrected, to perform normal integration.
COPYRIGHT: (C)1980,JPO&Japio
JP7975778A 1978-07-03 1978-07-03 Pulse integration method Pending JPS559205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7975778A JPS559205A (en) 1978-07-03 1978-07-03 Pulse integration method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7975778A JPS559205A (en) 1978-07-03 1978-07-03 Pulse integration method

Publications (1)

Publication Number Publication Date
JPS559205A true JPS559205A (en) 1980-01-23

Family

ID=13699088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7975778A Pending JPS559205A (en) 1978-07-03 1978-07-03 Pulse integration method

Country Status (1)

Country Link
JP (1) JPS559205A (en)

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