JPS559235A - Micro programming system - Google Patents

Micro programming system

Info

Publication number
JPS559235A
JPS559235A JP8062578A JP8062578A JPS559235A JP S559235 A JPS559235 A JP S559235A JP 8062578 A JP8062578 A JP 8062578A JP 8062578 A JP8062578 A JP 8062578A JP S559235 A JPS559235 A JP S559235A
Authority
JP
Japan
Prior art keywords
code
address
converter
instruction
programming system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8062578A
Other languages
Japanese (ja)
Inventor
Tadamitsu Ryu
Yuji Yoshida
Kiyoshi Washida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8062578A priority Critical patent/JPS559235A/en
Publication of JPS559235A publication Critical patent/JPS559235A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain the micro programming system which can independently be controlled for the internal operation, by coverting the instruction code from external unit into the sequence address code of the memory unit with the code converter.
CONSTITUTION: This program constitution is simplified that it consists of the control section, EXIT processing and its subroutine, by excluding the routines related to interruption and managing programs conventionally provided. In place of the interruption function, the code converter 11 is provided at the interface section between the micro processor and the processing unit CPU, and keyboard KB. The converter 11 assigns the address code to the instruction code from CPU and KB in the order of them and performs code conversion. Further, the head address of the input instruction is read out by locating each operation routine in separate address, to operate the internal operation through independent formation, alteration and addition.
COPYRIGHT: (C)1980,JPO&Japio
JP8062578A 1978-07-03 1978-07-03 Micro programming system Pending JPS559235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8062578A JPS559235A (en) 1978-07-03 1978-07-03 Micro programming system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8062578A JPS559235A (en) 1978-07-03 1978-07-03 Micro programming system

Publications (1)

Publication Number Publication Date
JPS559235A true JPS559235A (en) 1980-01-23

Family

ID=13723526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8062578A Pending JPS559235A (en) 1978-07-03 1978-07-03 Micro programming system

Country Status (1)

Country Link
JP (1) JPS559235A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814236A (en) * 1981-07-20 1983-01-27 Usac Electronics Ind Co Ltd Serial interface controlling system
JPS6136846A (en) * 1984-07-30 1986-02-21 Nec Corp Program control system
JPS63226391A (en) * 1987-03-13 1988-09-21 松下電工株式会社 Reciprocating type electric razor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814236A (en) * 1981-07-20 1983-01-27 Usac Electronics Ind Co Ltd Serial interface controlling system
JPS6136846A (en) * 1984-07-30 1986-02-21 Nec Corp Program control system
JPS63226391A (en) * 1987-03-13 1988-09-21 松下電工株式会社 Reciprocating type electric razor

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