JPS559276A - Display unit - Google Patents

Display unit

Info

Publication number
JPS559276A
JPS559276A JP8168778A JP8168778A JPS559276A JP S559276 A JPS559276 A JP S559276A JP 8168778 A JP8168778 A JP 8168778A JP 8168778 A JP8168778 A JP 8168778A JP S559276 A JPS559276 A JP S559276A
Authority
JP
Japan
Prior art keywords
crt
memory
video information
graphic area
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8168778A
Other languages
Japanese (ja)
Inventor
Nobumasa Watanabe
Yoshiyasu Kikuchi
Tomoki Shiyudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP8168778A priority Critical patent/JPS559276A/en
Publication of JPS559276A publication Critical patent/JPS559276A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To enable to display in the form of flexibility for broader graphic area as a whole, by displaying arbitrary graphic area on each CRT of the display unit consisting of a plurality of CRT's in common use of the control section.
CONSTITUTION: The device controller 11 performs control for the CRT's 17-1... 17-4, memorizes the video information with the picture memory 13, and stores the address of the memory 13 to the picture memory address circuit 12. The video information from the memory 13 is branched with the distributor 14, the video information distributed is stored in a plurality of refresh memories 16-1...16-4, and the address of the memories is stored in the refresh memory address circuit 15. Further, CRT's 17-1...17-4 are provided in pair with the memories 16-1...16-4 to display the video information stored in each memory. Thus, arbitrary graphic area is displayed on each CRT, and the graphic area broader as a whole can be displayed with flexibility.
COPYRIGHT: (C)1980,JPO&Japio
JP8168778A 1978-07-04 1978-07-04 Display unit Pending JPS559276A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8168778A JPS559276A (en) 1978-07-04 1978-07-04 Display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8168778A JPS559276A (en) 1978-07-04 1978-07-04 Display unit

Publications (1)

Publication Number Publication Date
JPS559276A true JPS559276A (en) 1980-01-23

Family

ID=13753259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8168778A Pending JPS559276A (en) 1978-07-04 1978-07-04 Display unit

Country Status (1)

Country Link
JP (1) JPS559276A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59137986A (en) * 1983-01-21 1984-08-08 ヴイドコム　レントサ−ビス　ベ−．ヴエ−． Information display system
JPH026990A (en) * 1988-06-27 1990-01-11 Hitachi Ltd Memory address control circuit
US7012576B2 (en) * 1999-12-29 2006-03-14 Intel Corporation Intelligent display interface

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59137986A (en) * 1983-01-21 1984-08-08 ヴイドコム　レントサ−ビス　ベ−．ヴエ−． Information display system
JPH026990A (en) * 1988-06-27 1990-01-11 Hitachi Ltd Memory address control circuit
US7012576B2 (en) * 1999-12-29 2006-03-14 Intel Corporation Intelligent display interface

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