JPS5592954A - Error correction system - Google Patents

Error correction system

Info

Publication number
JPS5592954A
JPS5592954A JP16240978A JP16240978A JPS5592954A JP S5592954 A JPS5592954 A JP S5592954A JP 16240978 A JP16240978 A JP 16240978A JP 16240978 A JP16240978 A JP 16240978A JP S5592954 A JPS5592954 A JP S5592954A
Authority
JP
Japan
Prior art keywords
circuit
block
block error
exclusive
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16240978A
Other languages
Japanese (ja)
Inventor
Yutaka Kamiyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16240978A priority Critical patent/JPS5592954A/en
Publication of JPS5592954A publication Critical patent/JPS5592954A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To make it possible to correct a block error by providing a delay circuit stage and syndrome generating circuit stage consisting of an exclusive-OR circuit and a circuit making cross connections among feedback shift register composed of registers.
CONSTITUTION: Random positive integers are represented by (b) and (m) and (b)- bit parallel information is transmitted as unit block, block by block, in series to a maximum of (qm-1)/(q-1)[q=2b]. Of this data processing system, a system which corrects a block error consists of delay circuits 10-0 and 10-1 and syndrome generating circuit stage 5 composed of exclusive-OR circuit 16 and cross connection circuit 13 which makes a cross connection between "#0" and "#1" feedback registers 12-0 and 12-1 as many as (b), for example, when (b) is "2" and (m) is "3". A block error of input is corrected by the output of circuit 5.
COPYRIGHT: (C)1980,JPO&Japio
JP16240978A 1978-12-29 1978-12-29 Error correction system Pending JPS5592954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16240978A JPS5592954A (en) 1978-12-29 1978-12-29 Error correction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16240978A JPS5592954A (en) 1978-12-29 1978-12-29 Error correction system

Publications (1)

Publication Number Publication Date
JPS5592954A true JPS5592954A (en) 1980-07-14

Family

ID=15754048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16240978A Pending JPS5592954A (en) 1978-12-29 1978-12-29 Error correction system

Country Status (1)

Country Link
JP (1) JPS5592954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965914A (en) * 1982-10-07 1984-04-14 Sanyo Electric Co Ltd Error position detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965914A (en) * 1982-10-07 1984-04-14 Sanyo Electric Co Ltd Error position detecting circuit

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