JPS55951A - Clock supervisory system - Google Patents

Clock supervisory system

Info

Publication number
JPS55951A
JPS55951A JP7434378A JP7434378A JPS55951A JP S55951 A JPS55951 A JP S55951A JP 7434378 A JP7434378 A JP 7434378A JP 7434378 A JP7434378 A JP 7434378A JP S55951 A JPS55951 A JP S55951A
Authority
JP
Japan
Prior art keywords
signal
circuit
stopping
pulse
clock pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7434378A
Other languages
Japanese (ja)
Inventor
Takaomi Fukuyama
Shinichi Isobe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fanuc Corp
Original Assignee
Fanuc Corp
Fujitsu Fanuc Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fanuc Corp, Fujitsu Fanuc Ltd filed Critical Fanuc Corp
Priority to JP7434378A priority Critical patent/JPS55951A/en
Publication of JPS55951A publication Critical patent/JPS55951A/en
Pending legal-status Critical Current

Links

Landscapes

  • Safety Devices In Control Systems (AREA)
  • Numerical Control (AREA)

Abstract

PURPOSE: To prevent an accident attending on the operation of stopping clocks, by equipping a unit, which operates synchronizing with clock pulses, with FF performing inversion by clock pulses, a delay circuit, exclusive logic sum circuit, and supervisory circuit composed of LPF.
CONSTITUTION: In the numerical controller, clock pulse (a) obtained from the output pulse of oscillator 1 by waveform-shaping 2 is divided by FF7 and division signal (b) and signal (c) obtained from signal (b) through approximately 180° delay 9 are inputted to exclusive logic sum circuit 8. Output signal (d) of circuit 8 has its high-frequency component removed by LPF10 to obtaine signal (e). As a result, when pulse (a) under a constant supervision stops, alarm generating circuit 11 is operated to send out an alarm and also to turn servo system 4 OFF, thereby stopping work machine 5. The stop of clock pulses is therefore detected automatically and an accident caused by stopping pulses can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP7434378A 1978-06-20 1978-06-20 Clock supervisory system Pending JPS55951A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7434378A JPS55951A (en) 1978-06-20 1978-06-20 Clock supervisory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7434378A JPS55951A (en) 1978-06-20 1978-06-20 Clock supervisory system

Publications (1)

Publication Number Publication Date
JPS55951A true JPS55951A (en) 1980-01-07

Family

ID=13544373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7434378A Pending JPS55951A (en) 1978-06-20 1978-06-20 Clock supervisory system

Country Status (1)

Country Link
JP (1) JPS55951A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0659712A (en) * 1992-08-04 1994-03-04 Nisshinbo Ind Inc Table moving stopping device and method ion nc working device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0659712A (en) * 1992-08-04 1994-03-04 Nisshinbo Ind Inc Table moving stopping device and method ion nc working device

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