JPS5596723A - Receiving detection circuit - Google Patents

Receiving detection circuit

Info

Publication number
JPS5596723A
JPS5596723A JP464679A JP464679A JPS5596723A JP S5596723 A JPS5596723 A JP S5596723A JP 464679 A JP464679 A JP 464679A JP 464679 A JP464679 A JP 464679A JP S5596723 A JPS5596723 A JP S5596723A
Authority
JP
Japan
Prior art keywords
output
pulse
detection circuit
circuit
9khz
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP464679A
Other languages
Japanese (ja)
Other versions
JPS6021487B2 (en
Inventor
Noboru Someno
Michimasa Komatsubara
Masakatsu Toyoshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP464679A priority Critical patent/JPS6021487B2/en
Publication of JPS5596723A publication Critical patent/JPS5596723A/en
Publication of JPS6021487B2 publication Critical patent/JPS6021487B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PURPOSE: To prevent tuning to the side band of a short duration by delaying pulses which change a receiving state detection FF.
CONSTITUTION: When up switch Su is turned on, the count value of counter 31 is increased for every pulse P32, and receiving frequency fi is increased by steps of 9kHz. When scan advances and the receiving frequency becomes (fi-9kHz) to detect the side band of broadcast of frequency fi, output Q37 of detection circuit 37 is changed, however, output Q37 continues hardly to be 1 during delayed output pulse P55 of pulse forming circuit 55 because of a short duration of output Q37 of 1, and output Q54 of AND circuit 54 cannot be changed.
COPYRIGHT: (C)1980,JPO&Japio
JP464679A 1979-01-18 1979-01-18 Reception detection circuit Expired JPS6021487B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP464679A JPS6021487B2 (en) 1979-01-18 1979-01-18 Reception detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP464679A JPS6021487B2 (en) 1979-01-18 1979-01-18 Reception detection circuit

Publications (2)

Publication Number Publication Date
JPS5596723A true JPS5596723A (en) 1980-07-23
JPS6021487B2 JPS6021487B2 (en) 1985-05-28

Family

ID=11589721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP464679A Expired JPS6021487B2 (en) 1979-01-18 1979-01-18 Reception detection circuit

Country Status (1)

Country Link
JP (1) JPS6021487B2 (en)

Also Published As

Publication number Publication date
JPS6021487B2 (en) 1985-05-28

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