JPS5596730A - Electronic circuit - Google Patents

Electronic circuit

Info

Publication number
JPS5596730A
JPS5596730A JP542879A JP542879A JPS5596730A JP S5596730 A JPS5596730 A JP S5596730A JP 542879 A JP542879 A JP 542879A JP 542879 A JP542879 A JP 542879A JP S5596730 A JPS5596730 A JP S5596730A
Authority
JP
Japan
Prior art keywords
clock signal
time
phi
level
superposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP542879A
Other languages
Japanese (ja)
Inventor
Takeshi Sakai
Tsutomu Ogishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP542879A priority Critical patent/JPS5596730A/en
Publication of JPS5596730A publication Critical patent/JPS5596730A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01714—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by bootstrapping, i.e. by positive feed-back

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To shorten the time of superposition between the first and the second clock signals to prevent malfunction by lowering the second clock signal, which is obtained by inverting the first clock signal, immediately after the second clock signal reaches a prescribed level at the rise time. CONSTITUTION:The level of clock signal inversion phi rises to make transistor Q6 conductive, and the level of connection point P3 raised by bootstrap capacity C is pulled by fixed power source Vcc and starts lowering immediately. As a result, the time required for the rise of clock signal inversion phi becomes short, and the time of superposition between this signal and clock signal phi is reduced, so that the operation characteristic in a low frequency can be improved.
JP542879A 1979-01-18 1979-01-18 Electronic circuit Pending JPS5596730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP542879A JPS5596730A (en) 1979-01-18 1979-01-18 Electronic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP542879A JPS5596730A (en) 1979-01-18 1979-01-18 Electronic circuit

Publications (1)

Publication Number Publication Date
JPS5596730A true JPS5596730A (en) 1980-07-23

Family

ID=11610898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP542879A Pending JPS5596730A (en) 1979-01-18 1979-01-18 Electronic circuit

Country Status (1)

Country Link
JP (1) JPS5596730A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267853A3 (en) * 1986-11-13 1990-03-28 Fairchild Semiconductor Corporation High-speed, bootstrap driver circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0267853A3 (en) * 1986-11-13 1990-03-28 Fairchild Semiconductor Corporation High-speed, bootstrap driver circuit

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