JPS5597083A - Bubble memory gate driving circuit - Google Patents

Bubble memory gate driving circuit

Info

Publication number
JPS5597083A
JPS5597083A JP14775278A JP14775278A JPS5597083A JP S5597083 A JPS5597083 A JP S5597083A JP 14775278 A JP14775278 A JP 14775278A JP 14775278 A JP14775278 A JP 14775278A JP S5597083 A JPS5597083 A JP S5597083A
Authority
JP
Japan
Prior art keywords
circuit
current
value
gate pattern
driving circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14775278A
Other languages
Japanese (ja)
Other versions
JPS598903B2 (en
Inventor
Suketsugu Yamaguchi
Masaaki Okada
Koji Tsuchiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14775278A priority Critical patent/JPS598903B2/en
Publication of JPS5597083A publication Critical patent/JPS5597083A/en
Publication of JPS598903B2 publication Critical patent/JPS598903B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To secure the reduced value for the DC current which flows to the gate pattern when the driving circuit has some trouble by giving the serial inserting connection between the CR parallel circuit and the gate pattern and then supplying the driving pulse current, thus realizing the miniaturization of the circuit.
CONSTITUTION: The output featuring the cycle of 5μs and pulse duration of 200ns and given from pulse generator 3 is inverted through NAND circuit 4 and then supplied to transistor TR5. And the output of TR5 is applied to gate pattern 2 via CR parallel circuit 6. Circuit 6 features a large impedance to the DC current and a small impedance to the fixed pulse current each. Accordingly, in case TR5 keeps the ON state by some reason, the value of resistance 10 is set to the proper value for circuit 6. As a result, the value of the DC current can be reduced down to such level as not to give burning to pattern 2.
COPYRIGHT: (C)1980,JPO&Japio
JP14775278A 1978-12-01 1978-12-01 Bubble memory gate drive circuit Expired JPS598903B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14775278A JPS598903B2 (en) 1978-12-01 1978-12-01 Bubble memory gate drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14775278A JPS598903B2 (en) 1978-12-01 1978-12-01 Bubble memory gate drive circuit

Publications (2)

Publication Number Publication Date
JPS5597083A true JPS5597083A (en) 1980-07-23
JPS598903B2 JPS598903B2 (en) 1984-02-28

Family

ID=15437338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14775278A Expired JPS598903B2 (en) 1978-12-01 1978-12-01 Bubble memory gate drive circuit

Country Status (1)

Country Link
JP (1) JPS598903B2 (en)

Also Published As

Publication number Publication date
JPS598903B2 (en) 1984-02-28

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