JPS55971A - Integrated-circuit device - Google Patents

Integrated-circuit device

Info

Publication number
JPS55971A
JPS55971A JP11207978A JP11207978A JPS55971A JP S55971 A JPS55971 A JP S55971A JP 11207978 A JP11207978 A JP 11207978A JP 11207978 A JP11207978 A JP 11207978A JP S55971 A JPS55971 A JP S55971A
Authority
JP
Japan
Prior art keywords
circuit
arithmetic
power
supplied
scale integration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11207978A
Other languages
Japanese (ja)
Inventor
Jiro Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11207978A priority Critical patent/JPS55971A/en
Publication of JPS55971A publication Critical patent/JPS55971A/en
Pending legal-status Critical Current

Links

Landscapes

  • Direct Current Feeding And Distribution (AREA)
  • Power Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To obtain an integrated circuit device with low power consumption which realizes large-scale integration by separately providing external power supply terminals to power supply lines to the 1st and 2nd circuit parts.
CONSTITUTION: As for an integrated circuit device used for an electronic desk calculator, arithmetic circuit 6 and gate group 5 operating during arithmetic operation are provided to the 1st circuit part 13, and shift registers 1 and 2, control circuit 7, display unit 8, arithmetic process detection circuit 15, and gate circuit group 3, namely, memory, control, display, supervision, and detection function parts are separately provided to the 2nd circuit part 14. The 1st circuit part 13 is supplied with power only during arithmetic execution. As a result, circuit 15 makes a decision on the state of circuit 7 determining the arithmetic procedure and after the arithmetic ends, switch circuit 19 breaks the circuit of power line 17 to part 13. The 2nd circuit part 14 is supplied with power via power line 18. Consequently, the power consumption can be reduced and large-scale integration becomes possible.
COPYRIGHT: (C)1980,JPO&Japio
JP11207978A 1978-09-11 1978-09-11 Integrated-circuit device Pending JPS55971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11207978A JPS55971A (en) 1978-09-11 1978-09-11 Integrated-circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11207978A JPS55971A (en) 1978-09-11 1978-09-11 Integrated-circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP48036026A Division JPS49123229A (en) 1973-03-28 1973-03-28

Publications (1)

Publication Number Publication Date
JPS55971A true JPS55971A (en) 1980-01-07

Family

ID=14577545

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11207978A Pending JPS55971A (en) 1978-09-11 1978-09-11 Integrated-circuit device

Country Status (1)

Country Link
JP (1) JPS55971A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121666A (en) * 1982-01-13 1983-07-20 Hitachi Ltd Analog integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58121666A (en) * 1982-01-13 1983-07-20 Hitachi Ltd Analog integrated circuit

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