JPS5597632A - Key input device - Google Patents

Key input device

Info

Publication number
JPS5597632A
JPS5597632A JP451479A JP451479A JPS5597632A JP S5597632 A JPS5597632 A JP S5597632A JP 451479 A JP451479 A JP 451479A JP 451479 A JP451479 A JP 451479A JP S5597632 A JPS5597632 A JP S5597632A
Authority
JP
Japan
Prior art keywords
key switches
gate
pulse
row line
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP451479A
Other languages
Japanese (ja)
Inventor
Sadahiro Takuhara
Kazumi Kawashima
Minoru Ueda
Hirosuke Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP451479A priority Critical patent/JPS5597632A/en
Publication of JPS5597632A publication Critical patent/JPS5597632A/en
Pending legal-status Critical Current

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  • Input From Keyboards Or The Like (AREA)

Abstract

PURPOSE: To prevent previously the erroneous input caused by the simultaneous operation of the key switches along with addition of the gate and the inverter.
CONSTITUTION: In case both key switches 2b and 2f are operated simultaneously, pulse B emerging on one row line α is inverted via inverter 7α and then applied to AND gate 6β to be cut off. And pulse B emerging to the other row line β is inverted through inverter 7β and then applied to AND gate 6α to be cut off. Thus the simultaneous application of both output pulses B from lines α and β can be avoided to decoder 5, and at the same time no output is generated from either one of output lines aWp. When either one of key switches 2aW2p is operated correctly, only the row line to which operated key switches 2aW2p are connected conducts among AND gates 6αW7δ. And thus the conventional input pulse is applied to decoder 5.
COPYRIGHT: (C)1980,JPO&Japio
JP451479A 1979-01-18 1979-01-18 Key input device Pending JPS5597632A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP451479A JPS5597632A (en) 1979-01-18 1979-01-18 Key input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP451479A JPS5597632A (en) 1979-01-18 1979-01-18 Key input device

Publications (1)

Publication Number Publication Date
JPS5597632A true JPS5597632A (en) 1980-07-25

Family

ID=11586152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP451479A Pending JPS5597632A (en) 1979-01-18 1979-01-18 Key input device

Country Status (1)

Country Link
JP (1) JPS5597632A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5088933A (en) * 1973-12-10 1975-07-17
JPS517864A (en) * 1974-07-09 1976-01-22 Tamura Electric Works Ltd

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5088933A (en) * 1973-12-10 1975-07-17
JPS517864A (en) * 1974-07-09 1976-01-22 Tamura Electric Works Ltd

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