JPS5597635A - Sequence display unit - Google Patents

Sequence display unit

Info

Publication number
JPS5597635A
JPS5597635A JP546979A JP546979A JPS5597635A JP S5597635 A JPS5597635 A JP S5597635A JP 546979 A JP546979 A JP 546979A JP 546979 A JP546979 A JP 546979A JP S5597635 A JPS5597635 A JP S5597635A
Authority
JP
Japan
Prior art keywords
data
display
pattern
memory
sequence program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP546979A
Other languages
Japanese (ja)
Other versions
JPS622325B2 (en
Inventor
Toshihiko Yomogida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Koki KK
Original Assignee
Toyoda Koki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Koki KK filed Critical Toyoda Koki KK
Priority to JP546979A priority Critical patent/JPS5597635A/en
Publication of JPS5597635A publication Critical patent/JPS5597635A/en
Publication of JPS622325B2 publication Critical patent/JPS622325B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Position Input By Displaying (AREA)

Abstract

PURPOSE: To realize the display similar to the actual relay circuit diagram by generating the pattern data for display based on the display data and the sequence program data read to the pattern data generation circuit and then carrying out the data of the symbol pattern or the like.
CONSTITUTION: Display unit 2 displays the sequence program memorized in memory 10 or the like of sequence controller 1 in the form of the ladder diagram. And program read-in circuit 20 writes the sequence program and the ineffective display data into reading buffer memory 21 from memory 10. Then the pattern data for display is generated based on the display data and the program data read out and via the pattern data generation circuit consisting of refresh memory 22, character generator 23 and timing signal generation circuit 24 each. Thus the display is secured for the symbol pattern which cannot be displayed via the sequence program data. In this way, the pattern approximate to the actual relay circuit diagram can be displayed on the screen.
COPYRIGHT: (C)1980,JPO&Japio
JP546979A 1979-01-19 1979-01-19 Sequence display unit Granted JPS5597635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP546979A JPS5597635A (en) 1979-01-19 1979-01-19 Sequence display unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP546979A JPS5597635A (en) 1979-01-19 1979-01-19 Sequence display unit

Publications (2)

Publication Number Publication Date
JPS5597635A true JPS5597635A (en) 1980-07-25
JPS622325B2 JPS622325B2 (en) 1987-01-19

Family

ID=11612091

Family Applications (1)

Application Number Title Priority Date Filing Date
JP546979A Granted JPS5597635A (en) 1979-01-19 1979-01-19 Sequence display unit

Country Status (1)

Country Link
JP (1) JPS5597635A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598075A (en) * 1982-07-02 1984-01-17 Omron Tateisi Electronics Co Producer of circuit diagram for programmable controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS598075A (en) * 1982-07-02 1984-01-17 Omron Tateisi Electronics Co Producer of circuit diagram for programmable controller

Also Published As

Publication number Publication date
JPS622325B2 (en) 1987-01-19

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