JPS5597764A - Decoding circuit for dmi code - Google Patents

Decoding circuit for dmi code

Info

Publication number
JPS5597764A
JPS5597764A JP514479A JP514479A JPS5597764A JP S5597764 A JPS5597764 A JP S5597764A JP 514479 A JP514479 A JP 514479A JP 514479 A JP514479 A JP 514479A JP S5597764 A JPS5597764 A JP S5597764A
Authority
JP
Japan
Prior art keywords
circuit
circuits
signal
integrating
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP514479A
Other languages
Japanese (ja)
Other versions
JPS6337990B2 (en
Inventor
Toshikazu Matsumoto
Risuke Shimodaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP514479A priority Critical patent/JPS5597764A/en
Publication of JPS5597764A publication Critical patent/JPS5597764A/en
Publication of JPS6337990B2 publication Critical patent/JPS6337990B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To discriminate between a data signal and error signal of a string of pulses of two systems by integrating by integrating circuits out-of-phase signals of two systems dicriminated by a read circuit, and then by controlling a switch circuit by signals obtained by integrating. CONSTITUTION:A DMI signal from input terminal 1 is delayed by delay circuit 5 by as many as fixed time slots and then converted into a binary ZR signal by exclusive-OR circuit 6, and clocks from input terminal 2 are applied to discrimination circuits 8 and 9 through clock distributor circuit 7. Then, the output of circuit 6 is applied to discrimination circuits 8 and 9 and signals of two systems discriminated by circuits 8 and 9 are supplied to switch circuit 13 and also to integrating circuits 10 and 11; and circuit 13 is controlled through switch control circuit 12 by integral signals obtained by those circuits 10 and 11 and circuit 13 discriminates between an error signal and data signal of the DMI signal from terminal 1.
JP514479A 1979-01-19 1979-01-19 Decoding circuit for dmi code Granted JPS5597764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP514479A JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP514479A JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Publications (2)

Publication Number Publication Date
JPS5597764A true JPS5597764A (en) 1980-07-25
JPS6337990B2 JPS6337990B2 (en) 1988-07-27

Family

ID=11603098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP514479A Granted JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Country Status (1)

Country Link
JP (1) JPS5597764A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (en) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> Code transmitting system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244108A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Code error detection equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244108A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Code error detection equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (en) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> Code transmitting system

Also Published As

Publication number Publication date
JPS6337990B2 (en) 1988-07-27

Similar Documents

Publication Publication Date Title
AU577336B2 (en) Regenerating the significant instants of a periodic signal
GB1533577A (en) Synchronising means
JPS5758214A (en) Forming circuit of data sampling clock
GB1461844A (en) Alarm device
JPS5710566A (en) Decoding circuit
JPS5799841A (en) Automatic signal phase matching circuit
JPS57106264A (en) System for data reproducing
RU2006955C1 (en) System for remote control of controlled object
JPS56131245A (en) Signal detecting circuit
SU1022205A1 (en) Device for receiving telecontrol instructions
JPS57136845A (en) Coding and transfer system of information data
SU902302A1 (en) Digital information receiving device
JPS56110130A (en) Priority concurrent circuit
SU1077050A1 (en) Device for majority decoding of binary codes
SU1727200A1 (en) Device for conversion of series code to parallel code
SU1010717A1 (en) Pseudorandom train generator
SU1396255A1 (en) Device for shaping relative bipulse signal
SU1347189A1 (en) Code converter
JPS5744329A (en) Control signal generating circuit
SU1325454A1 (en) Multichannel device for time shift of coincidence pulses
SU1522409A1 (en) Decoder
SU616646A1 (en) Remote control information transmitter
SU1646077A1 (en) Device for separation of code combination
JPS5679546A (en) Data transmission system
JPS5789364A (en) Pulse signal regenerative repeating installation