JPS5597767A - Mixing adder-subtracter circuit - Google Patents

Mixing adder-subtracter circuit

Info

Publication number
JPS5597767A
JPS5597767A JP497379A JP497379A JPS5597767A JP S5597767 A JPS5597767 A JP S5597767A JP 497379 A JP497379 A JP 497379A JP 497379 A JP497379 A JP 497379A JP S5597767 A JPS5597767 A JP S5597767A
Authority
JP
Japan
Prior art keywords
impedance
load
signal source
signal
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP497379A
Other languages
Japanese (ja)
Other versions
JPS6260848B2 (en
Inventor
Hitoshi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP497379A priority Critical patent/JPS5597767A/en
Publication of JPS5597767A publication Critical patent/JPS5597767A/en
Publication of JPS6260848B2 publication Critical patent/JPS6260848B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/58—Anti-side-tone circuits
    • H04M1/585—Anti-side-tone circuits implemented without inductive element

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To reduce the attenuation value of an input signal by reducing the insertion loss of impedance by connecting impedance in series to the load of a 1st signal source and then by connecting an emitter follower amplifier to this impedance. CONSTITUTION:Mixing impedance Z2 is connected in series to load Z1 of 1st signal source V1, and emitter follower amplifying transistor Tr is also connected to impedance Z2. Further, 2nd signal source V2 is connected to the base of this amplifying Tr to constitute a mixing adder-subtracter circuit. Now, a signal current from signal source V1 is flowed to load Z1 and impedance Z2 and variation in voltage appearing across impedance Z2 is supplied between the base and emitter of amplifying Tr; and its collector current is varied by increasing or decreasing a load current and the effective impedance of impedance Z2, thereby lessening the insertion loss of impedance Z2. In addition, a signal from signal source V2 is mixed as an emitter load into impedance Z2 by superposing.
JP497379A 1979-01-19 1979-01-19 Mixing adder-subtracter circuit Granted JPS5597767A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP497379A JPS5597767A (en) 1979-01-19 1979-01-19 Mixing adder-subtracter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP497379A JPS5597767A (en) 1979-01-19 1979-01-19 Mixing adder-subtracter circuit

Publications (2)

Publication Number Publication Date
JPS5597767A true JPS5597767A (en) 1980-07-25
JPS6260848B2 JPS6260848B2 (en) 1987-12-18

Family

ID=11598533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP497379A Granted JPS5597767A (en) 1979-01-19 1979-01-19 Mixing adder-subtracter circuit

Country Status (1)

Country Link
JP (1) JPS5597767A (en)

Also Published As

Publication number Publication date
JPS6260848B2 (en) 1987-12-18

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