JPS5599626A - Bus line cutting system - Google Patents

Bus line cutting system

Info

Publication number
JPS5599626A
JPS5599626A JP625179A JP625179A JPS5599626A JP S5599626 A JPS5599626 A JP S5599626A JP 625179 A JP625179 A JP 625179A JP 625179 A JP625179 A JP 625179A JP S5599626 A JPS5599626 A JP S5599626A
Authority
JP
Japan
Prior art keywords
logic
signal
bus
receiver
bus line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP625179A
Other languages
Japanese (ja)
Inventor
Shunji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Yokogawa Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp, Yokogawa Electric Works Ltd filed Critical Yokogawa Hokushin Electric Corp
Priority to JP625179A priority Critical patent/JPS5599626A/en
Publication of JPS5599626A publication Critical patent/JPS5599626A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To realize the free cutting of the bus line by inserting the tristate logic intermission which operates on the fixed control and driving signals plus the driver receiver into the bus line.
CONSTITUTION: Control signal C1 of logic 1 is supplied to input terminal 31A of tristate logic circuit 31, and at the same time control signal C2 of logic 0 is applied to input terminal 32A of driver receiver 32 each. Each output of circuit 31 features a high impedance and is cut off from bus 1. With application of driving signal RD, buses 1 and 2 are connected together for receiver 32 to perform the signal transmission at the steady time. Then if logic 1 is applied to signal C2, the input end of receiver 32 features a high impedance. Thus bus 1 is cut off from bus 2 substantially. While if logic 0 and signal RD are applied to signal C2, circuit 31 is connected to bus 1. In such way, the free intermission is secured between buses 1 and 2, thus realizing the fault diagnosis via the code analysis method.
COPYRIGHT: (C)1980,JPO&Japio
JP625179A 1979-01-22 1979-01-22 Bus line cutting system Pending JPS5599626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP625179A JPS5599626A (en) 1979-01-22 1979-01-22 Bus line cutting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP625179A JPS5599626A (en) 1979-01-22 1979-01-22 Bus line cutting system

Publications (1)

Publication Number Publication Date
JPS5599626A true JPS5599626A (en) 1980-07-29

Family

ID=11633261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP625179A Pending JPS5599626A (en) 1979-01-22 1979-01-22 Bus line cutting system

Country Status (1)

Country Link
JP (1) JPS5599626A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201126A (en) * 1983-04-28 1984-11-14 Nec Corp Common bus control system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286727A (en) * 1975-12-23 1977-07-19 Okura Denki Co Ltd System for forming bus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5286727A (en) * 1975-12-23 1977-07-19 Okura Denki Co Ltd System for forming bus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201126A (en) * 1983-04-28 1984-11-14 Nec Corp Common bus control system

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