JPS5599663A - Program recording circuit - Google Patents

Program recording circuit

Info

Publication number
JPS5599663A
JPS5599663A JP627179A JP627179A JPS5599663A JP S5599663 A JPS5599663 A JP S5599663A JP 627179 A JP627179 A JP 627179A JP 627179 A JP627179 A JP 627179A JP S5599663 A JPS5599663 A JP S5599663A
Authority
JP
Japan
Prior art keywords
circuit
program
interruption
block
memorized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP627179A
Other languages
Japanese (ja)
Inventor
Yasuyuki Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP627179A priority Critical patent/JPS5599663A/en
Publication of JPS5599663A publication Critical patent/JPS5599663A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To obtain the using frequency of the program block in a simple way by installing the fixed program memory circuit to the CPU possessing the interruption circuit incorporating the watchdog timer.
CONSTITUTION: Program memory circuit PRC consisting of random number generation circuit RG, order counter reading circuit ADR, program type reading circuit PID and data memory means ME each is installed to the CPU possessing interruption circuit incorporating watchdog timer WT. Then at the time interruption point, the value of order counter IC plus the block name of the program under being executed are read via circuits ADR and PID to be then memorized in means ME. At the same time, the time to generate the next interruption is obtained through circuit RG, and the value obtained is set to timer WT. This action is repeated to be memorized into means ME. And based on the memory contents, the using frequency can be obtained in a simple way for the block of the desired program.
COPYRIGHT: (C)1980,JPO&Japio
JP627179A 1979-01-22 1979-01-22 Program recording circuit Pending JPS5599663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP627179A JPS5599663A (en) 1979-01-22 1979-01-22 Program recording circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP627179A JPS5599663A (en) 1979-01-22 1979-01-22 Program recording circuit

Publications (1)

Publication Number Publication Date
JPS5599663A true JPS5599663A (en) 1980-07-29

Family

ID=11633752

Family Applications (1)

Application Number Title Priority Date Filing Date
JP627179A Pending JPS5599663A (en) 1979-01-22 1979-01-22 Program recording circuit

Country Status (1)

Country Link
JP (1) JPS5599663A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320548A (en) * 1991-04-20 1992-11-11 Fujitsu Ltd Execution unit load analyzing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04320548A (en) * 1991-04-20 1992-11-11 Fujitsu Ltd Execution unit load analyzing system

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