JPS56100526A - Adaptive phase synchronizing circuit - Google Patents

Adaptive phase synchronizing circuit

Info

Publication number
JPS56100526A
JPS56100526A JP339580A JP339580A JPS56100526A JP S56100526 A JPS56100526 A JP S56100526A JP 339580 A JP339580 A JP 339580A JP 339580 A JP339580 A JP 339580A JP S56100526 A JPS56100526 A JP S56100526A
Authority
JP
Japan
Prior art keywords
input
phase
circuit
synchronizing circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP339580A
Other languages
Japanese (ja)
Other versions
JPS5945297B2 (en
Inventor
Hideo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55003395A priority Critical patent/JPS5945297B2/en
Publication of JPS56100526A publication Critical patent/JPS56100526A/en
Publication of JPS5945297B2 publication Critical patent/JPS5945297B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To minimize noise electric power caused by phase jitter and input noise, by controlling parameters of the phase synchronizing circuit digitally. CONSTITUTION:The input signal input from terminal 1 is input to phase comparing circuit 2 together with the output signal of variable frequency oscillating circuit 4, and a phase error signal is output. This phase error signal is applied to oscillating circuit 4 through loop filter 3 to control the phase of output signal and is input to coefficient controlling circuit 7 which outputs coefficient values to loop filter 3 and digital filter 5.
JP55003395A 1980-01-16 1980-01-16 Adaptive phase locked circuit Expired JPS5945297B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55003395A JPS5945297B2 (en) 1980-01-16 1980-01-16 Adaptive phase locked circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55003395A JPS5945297B2 (en) 1980-01-16 1980-01-16 Adaptive phase locked circuit

Publications (2)

Publication Number Publication Date
JPS56100526A true JPS56100526A (en) 1981-08-12
JPS5945297B2 JPS5945297B2 (en) 1984-11-05

Family

ID=11556166

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55003395A Expired JPS5945297B2 (en) 1980-01-16 1980-01-16 Adaptive phase locked circuit

Country Status (1)

Country Link
JP (1) JPS5945297B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115379A (en) * 1981-12-29 1983-07-09 Fujitsu Ltd Phase-lock type receiver of hyperbolic navigation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58115379A (en) * 1981-12-29 1983-07-09 Fujitsu Ltd Phase-lock type receiver of hyperbolic navigation

Also Published As

Publication number Publication date
JPS5945297B2 (en) 1984-11-05

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