JPS56100571A - Facsimile transmitter - Google Patents
Facsimile transmitterInfo
- Publication number
- JPS56100571A JPS56100571A JP419180A JP419180A JPS56100571A JP S56100571 A JPS56100571 A JP S56100571A JP 419180 A JP419180 A JP 419180A JP 419180 A JP419180 A JP 419180A JP S56100571 A JPS56100571 A JP S56100571A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- significant signal
- level
- signal
- subscanning
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
- H04N1/17—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa the scanning speed being dependent on content of picture
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Editing Of Facsimile Originals (AREA)
- Facsimile Scanning Arrangements (AREA)
Abstract
PURPOSE:To perform detection operation of a significant signal with the same precision constantly, by detecting presence or absence of the significant signal and by generating a pulse for subscanning driving at the prescribed timing according to presence or absence of the significant signal. CONSTITUTION:If a significant signal does not exist in the led-out picture signal, outputs DA and DB of deciding circuit 4 become low-level, and buffer memory 13 is held in the write state continuously and waits for the write of the picture signal led out from binary circuit 3 the next period. At a fixed time after the output of counting circuit 6 is switched to the low level, motor control circuit 11 generates subscanning driving pulse. If the significant signal exists, outputs of deciding circuit 4 become high-level together, and write and read of buffer memory 13 are inhibited. Motor control circuit 11 does not generate the subscanning driving pulse. Circuit 11 generates the driving pulse at the timing of the rise of the first phase signal DA when one side output DB becomes low-level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP419180A JPS56100571A (en) | 1980-01-17 | 1980-01-17 | Facsimile transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP419180A JPS56100571A (en) | 1980-01-17 | 1980-01-17 | Facsimile transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56100571A true JPS56100571A (en) | 1981-08-12 |
| JPS6210466B2 JPS6210466B2 (en) | 1987-03-06 |
Family
ID=11577799
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP419180A Granted JPS56100571A (en) | 1980-01-17 | 1980-01-17 | Facsimile transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56100571A (en) |
-
1980
- 1980-01-17 JP JP419180A patent/JPS56100571A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6210466B2 (en) | 1987-03-06 |
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