JPS56107632A - Phase comparing circuit - Google Patents
Phase comparing circuitInfo
- Publication number
- JPS56107632A JPS56107632A JP973280A JP973280A JPS56107632A JP S56107632 A JPS56107632 A JP S56107632A JP 973280 A JP973280 A JP 973280A JP 973280 A JP973280 A JP 973280A JP S56107632 A JPS56107632 A JP S56107632A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- terminal
- clock
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- G01R25/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
PURPOSE:To expand the operation range by making it possible to obtain the phase comparison output even in the period of pulse width of the reset pulse in the phase comparator circuit for which the FF is used. CONSTITUTION:The input clock which has been provided to the terminal 11 is applied to the reset terminal R of the FF13 after its rise has been detected by the rise detecting circuit 12. Also, the output clock which has been provided to the terminal 22 is applied to the clock terminal C of the FF13, a signal of pulse width corresponding to the phase difference of the input/output clocks is output from the terminal Q', and it is applied to the switching circuit 20. Moreover, the input/ output clocks are applied to the exclusive ''or'' circuit 14 and the logical product circuit 15, and the outputs are also applied to the switching circuit 20. On the other hand, the FF19 is set and reset in case when the output clock is ''1'' and ''0'', respectively, when there is an output of the rise detecting circuit 12. And, the switching circuit 20 selects an output of the logical product circut 15 and an output of the FF13, in case when the output of the FF19 is ''1'', and ''0'', respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP973280A JPS56107632A (en) | 1980-01-30 | 1980-01-30 | Phase comparing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP973280A JPS56107632A (en) | 1980-01-30 | 1980-01-30 | Phase comparing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56107632A true JPS56107632A (en) | 1981-08-26 |
Family
ID=11728478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP973280A Pending JPS56107632A (en) | 1980-01-30 | 1980-01-30 | Phase comparing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56107632A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234717A (en) * | 1987-03-24 | 1988-09-30 | Nec Corp | Phase comparing circuit |
| US6959061B1 (en) | 1998-10-07 | 2005-10-25 | Fujitsu Limited | Phase comparator circuit |
-
1980
- 1980-01-30 JP JP973280A patent/JPS56107632A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63234717A (en) * | 1987-03-24 | 1988-09-30 | Nec Corp | Phase comparing circuit |
| US6959061B1 (en) | 1998-10-07 | 2005-10-25 | Fujitsu Limited | Phase comparator circuit |
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