JPS56108246A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56108246A JPS56108246A JP1183980A JP1183980A JPS56108246A JP S56108246 A JPS56108246 A JP S56108246A JP 1183980 A JP1183980 A JP 1183980A JP 1183980 A JP1183980 A JP 1183980A JP S56108246 A JPS56108246 A JP S56108246A
- Authority
- JP
- Japan
- Prior art keywords
- sio2
- film
- metal
- polycrystalline
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/59—Bond pads specially adapted therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/921—Structures or relative sizes of bond pads
- H10W72/923—Bond pads having multiple stacked layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/981—Auxiliary members, e.g. spacers
- H10W72/983—Reinforcing structures, e.g. collars
Landscapes
- Wire Bonding (AREA)
Abstract
PURPOSE:To prevent the destruction of the SiO2 film in a semiconductor device due to shock in wire bonding and obtain a bonding pad having a small parasitic capacity by successively placing a plurality of sets of combination of a conductive layer and an SiO2 layer between the insulating film on the semiconductor substrate surface and the metal film on which wire bonding is performed. CONSTITUTION:On the SiO2 film 2 on a substrate 1, a polycrystalline Si conductive layer 5 is provided and oxidized at high temperature so as to be coated with SiO2 6. Moreover, a polycrystalline Si conductive layer 7 is piled thereon and coated with SiO2 8, then a metal 3a is piled thereon and providied with a protective film. By said constitution, when wire bonding is performed on the metal 3a, the shock to the SiO2 film 2 is reduced because it is absorbed and dispersed by the conductive layers 6 and 7. Accordingly, if thin, the SiO2 film 2 is not destroyed. Also, instead of polycrystalline Si, a metal having high melting point such as Mo or molybdenum silicide and an insulator can be used. Moreover, by said constitution, because the insulating layers 6 and 8 are placed between the substrate 1 and the metal layer 3a, the parasitic capacity decreases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1183980A JPS56108246A (en) | 1980-02-01 | 1980-02-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1183980A JPS56108246A (en) | 1980-02-01 | 1980-02-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS56108246A true JPS56108246A (en) | 1981-08-27 |
Family
ID=11788891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1183980A Pending JPS56108246A (en) | 1980-02-01 | 1980-02-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56108246A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181041A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor integrated circuit device |
-
1980
- 1980-02-01 JP JP1183980A patent/JPS56108246A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181041A (en) * | 1983-03-31 | 1984-10-15 | Toshiba Corp | Semiconductor integrated circuit device |
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