JPS5611559A - Separating unit for closed loop graph - Google Patents

Separating unit for closed loop graph

Info

Publication number
JPS5611559A
JPS5611559A JP8720079A JP8720079A JPS5611559A JP S5611559 A JPS5611559 A JP S5611559A JP 8720079 A JP8720079 A JP 8720079A JP 8720079 A JP8720079 A JP 8720079A JP S5611559 A JPS5611559 A JP S5611559A
Authority
JP
Japan
Prior art keywords
memory
conversion
circuit
information
closed loop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8720079A
Other languages
Japanese (ja)
Inventor
Masumi Yoshida
Takeshi Masui
Shigemi Osada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8720079A priority Critical patent/JPS5611559A/en
Publication of JPS5611559A publication Critical patent/JPS5611559A/en
Pending legal-status Critical Current

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  • Editing Of Facsimile Originals (AREA)
  • Image Analysis (AREA)

Abstract

PURPOSE: To pick up the closed loop in high speed, by ensuring to pick up the closed loop graph through repetition of one dimensional scanning, and using the minimum video memory and the 0→1 conversion and 1→0 conversion circuits through the pipeline processing.
CONSTITUTION: The input video signal is stored in the #0 video memory 14, the content of the memory 14 is read out every one scanning line at the scanning mode of the horizontal direction upper to lower order by the instruction of the total control section 19, it is processed at the 0→1 conversion circuit 17, and the 0→1 converted video information is written in the #1 video memory 15. Next, the information written in the memory 15 is read out with the scanning mode of horizontal direction lower to upper order, it is fed to the 1→0 conversion circuit 18, and the information on the memory 14 is fed to the circuit 18. Further, the 1→0 conversion video information processed at the circuit 18 is written in the #2 video memory 16, and the information is read out at the scanning mode of vertical direction left to right order and fed to the circuit 18. This operation is repeated while being monitored at the deviation calculation circuit 23, and the 1→0 conversion video information is picked up from the closed loop in high speed.
COPYRIGHT: (C)1981,JPO&Japio
JP8720079A 1979-07-10 1979-07-10 Separating unit for closed loop graph Pending JPS5611559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8720079A JPS5611559A (en) 1979-07-10 1979-07-10 Separating unit for closed loop graph

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8720079A JPS5611559A (en) 1979-07-10 1979-07-10 Separating unit for closed loop graph

Publications (1)

Publication Number Publication Date
JPS5611559A true JPS5611559A (en) 1981-02-04

Family

ID=13908322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8720079A Pending JPS5611559A (en) 1979-07-10 1979-07-10 Separating unit for closed loop graph

Country Status (1)

Country Link
JP (1) JPS5611559A (en)

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