JPS56129949A - Address comparison system - Google Patents

Address comparison system

Info

Publication number
JPS56129949A
JPS56129949A JP3244180A JP3244180A JPS56129949A JP S56129949 A JPS56129949 A JP S56129949A JP 3244180 A JP3244180 A JP 3244180A JP 3244180 A JP3244180 A JP 3244180A JP S56129949 A JPS56129949 A JP S56129949A
Authority
JP
Japan
Prior art keywords
address
control
physical address
address register
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3244180A
Other languages
Japanese (ja)
Inventor
Tsuguo Ueki
Nobuyuki Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3244180A priority Critical patent/JPS56129949A/en
Publication of JPS56129949A publication Critical patent/JPS56129949A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To simplify the readout control means and to increase the processing speed, by comparing the address input to the physical address register with the address input to the specific region. CONSTITUTION:In case of control at virtual address mode, if the request to memory is present, the logic address is input to the logic address register 1 and the page part is set to the page section of the physical address register 12. In this case, the in-page address part of the virtual address is set to the in-page section in the physical address register 12. Further, it is compared with the physical address in the specific area of the comparison address register 11 at the comparator 8, and when in agreement, the control signal is produced and control is made. Further, in the control of real address mode, since the physical address is input to the logic address register 1, the page part of this physical address is set to the physical address register 12 as it is, allowing similar comparison control.
JP3244180A 1980-03-14 1980-03-14 Address comparison system Pending JPS56129949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3244180A JPS56129949A (en) 1980-03-14 1980-03-14 Address comparison system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3244180A JPS56129949A (en) 1980-03-14 1980-03-14 Address comparison system

Publications (1)

Publication Number Publication Date
JPS56129949A true JPS56129949A (en) 1981-10-12

Family

ID=12359041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3244180A Pending JPS56129949A (en) 1980-03-14 1980-03-14 Address comparison system

Country Status (1)

Country Link
JP (1) JPS56129949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143338A (en) * 1988-11-24 1990-06-01 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02143338A (en) * 1988-11-24 1990-06-01 Nec Corp Information processor

Similar Documents

Publication Publication Date Title
KR850700279A (en) Computer and its improvement
JPS5464439A (en) Address designation system
JPS56129949A (en) Address comparison system
JPS5319728A (en) Data treansfer processing system
JPS5334429A (en) Memory control system
JPS5482140A (en) Information processor
JPS5474632A (en) Data processor
JPS5555490A (en) Memory control system
JPS57108952A (en) Busy control system
JPS559228A (en) Memory request control system
JPS5415620A (en) Buffer memory unit
JPS5599656A (en) Interruption processor
JPS54128640A (en) Control system for cash memory
JPS5616982A (en) Buffer memory control system
JPS53107240A (en) Control system of register memory
JPS54128639A (en) Control system for cash memory
JPS57111871A (en) Buffer storage control system
JPS57109177A (en) List processing system
JPS56153459A (en) Bank memory control system
JPS57101945A (en) Control system of information processor
JPS5785162A (en) Picture memory access control system
JPS5798176A (en) Storage controlling unit
JPS55108984A (en) Memorieed information read system
JPS57159348A (en) Microprogram control system
JPS5462735A (en) Memory control system