JPS56129962A - Monitor system for system failure - Google Patents

Monitor system for system failure

Info

Publication number
JPS56129962A
JPS56129962A JP3219280A JP3219280A JPS56129962A JP S56129962 A JPS56129962 A JP S56129962A JP 3219280 A JP3219280 A JP 3219280A JP 3219280 A JP3219280 A JP 3219280A JP S56129962 A JPS56129962 A JP S56129962A
Authority
JP
Japan
Prior art keywords
monitor
processor
reset signal
output
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3219280A
Other languages
Japanese (ja)
Inventor
Susumu Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3219280A priority Critical patent/JPS56129962A/en
Publication of JPS56129962A publication Critical patent/JPS56129962A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To enable to detect a system failure accurately and quickly, by constituting a test start signal is output if a reset signal is not received by the timer within a given time, in a computer system consisting of processor and monitor. CONSTITUTION:When the monitor start signal is fed to the timer 21 of the monitor 20 by the processor 10, the time counter 21a starts counting. After that, the reset signal is output every given time from the reset signal generating circuit 11 in the processor 10, the counter 21a is reset, and counting is again started. If no reset signal is delivered after a given time, overflow is caused to the counter 21a. The detection circuit 21b detects the overflow and the test start signal of the processor 10 is output to the diagnostic circuit in the monitor 20.
JP3219280A 1980-03-14 1980-03-14 Monitor system for system failure Pending JPS56129962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3219280A JPS56129962A (en) 1980-03-14 1980-03-14 Monitor system for system failure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3219280A JPS56129962A (en) 1980-03-14 1980-03-14 Monitor system for system failure

Publications (1)

Publication Number Publication Date
JPS56129962A true JPS56129962A (en) 1981-10-12

Family

ID=12352033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3219280A Pending JPS56129962A (en) 1980-03-14 1980-03-14 Monitor system for system failure

Country Status (1)

Country Link
JP (1) JPS56129962A (en)

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