JPS5614330A - Data processing system - Google Patents

Data processing system

Info

Publication number
JPS5614330A
JPS5614330A JP9021179A JP9021179A JPS5614330A JP S5614330 A JPS5614330 A JP S5614330A JP 9021179 A JP9021179 A JP 9021179A JP 9021179 A JP9021179 A JP 9021179A JP S5614330 A JPS5614330 A JP S5614330A
Authority
JP
Japan
Prior art keywords
transfer
master
circuit
output
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9021179A
Other languages
Japanese (ja)
Inventor
Yutaka Onodera
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9021179A priority Critical patent/JPS5614330A/en
Publication of JPS5614330A publication Critical patent/JPS5614330A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To perform effective transfer of busses, by providing a data processing system including the response function to reduce the increase of bus traffic due to the upon meaningless bus transfer retry of the master in case of asynchronous conversation type bus transfer.
CONSTITUTION: The output of AND circuit 60-1 of the circuit which decodes the response signal and the status signal output from the slave indicates that transfer from the master has been accepted by the slave. Next, in case that the output of AND circuit 60-2 is "1", response signal BSACKR-, status signal BSWAIT-, and BSNARK- are "0", "1", and "0", respectively, and it is indicated that transfer from the master has been rejected. Further, when the output of AND circuit 60-3 is "1", response signal BSACKR- and status signal BSNARK- are "1" and "0" respectively, and it is indicated that the slave designated by the master does not exist. Thus, bus traffic due to the meaningless bus transfer retry of the master can be reduced to perform effective transfer of busses.
COPYRIGHT: (C)1981,JPO&Japio
JP9021179A 1979-07-16 1979-07-16 Data processing system Pending JPS5614330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9021179A JPS5614330A (en) 1979-07-16 1979-07-16 Data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9021179A JPS5614330A (en) 1979-07-16 1979-07-16 Data processing system

Publications (1)

Publication Number Publication Date
JPS5614330A true JPS5614330A (en) 1981-02-12

Family

ID=13992142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9021179A Pending JPS5614330A (en) 1979-07-16 1979-07-16 Data processing system

Country Status (1)

Country Link
JP (1) JPS5614330A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5065144A (en) * 1973-10-11 1975-06-02
JPS5123046A (en) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS5211837A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Input-output interface starting method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5065144A (en) * 1973-10-11 1975-06-02
JPS5123046A (en) * 1974-08-21 1976-02-24 Hitachi Ltd
JPS5211837A (en) * 1975-07-18 1977-01-29 Hitachi Ltd Input-output interface starting method

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