JPS5614955A - Power-factor detection circuit - Google Patents

Power-factor detection circuit

Info

Publication number
JPS5614955A
JPS5614955A JP9123179A JP9123179A JPS5614955A JP S5614955 A JPS5614955 A JP S5614955A JP 9123179 A JP9123179 A JP 9123179A JP 9123179 A JP9123179 A JP 9123179A JP S5614955 A JPS5614955 A JP S5614955A
Authority
JP
Japan
Prior art keywords
signal
rectified
power
factor
generate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9123179A
Other languages
Japanese (ja)
Inventor
Kenzo Akamatsu
Tadashi Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP9123179A priority Critical patent/JPS5614955A/en
Publication of JPS5614955A publication Critical patent/JPS5614955A/en
Pending legal-status Critical Current

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  • Measurement Of Current Or Voltage (AREA)

Abstract

PURPOSE: To accurately detect a power-factor, by combining the positive and negative rectified waves of a sinusoidal voltage signal with each other depending on a logical level signal generated by converting a current signal.
CONSTITUTION: The positive and negative portions of a sinusoidal voltage signal 1a are rectified to obtain rectified waves 1b, 2b. The wave form of a current signal 4a having a phase difference of ϕ from the voltage signal is changed at 4 to generate a logical level signal 4b. The rectified signals 1b, 2a are synthesized at 3 with each other depending on the logical level signal 4b. For example, the polarity of the rectified signal 2a is inverted for a time t1Wt2 to perform the synthesis. The rectified signals 1b, 2a are smoothed and averaged at 5 to generate a signal 5a. The synthesized signal 3a is divided by the signal 5a to generate a signal 6a corresponding to the power-factor of cosϕ. This results in accurately detecting the power-factor through a simple construction.
COPYRIGHT: (C)1981,JPO&Japio
JP9123179A 1979-07-17 1979-07-17 Power-factor detection circuit Pending JPS5614955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9123179A JPS5614955A (en) 1979-07-17 1979-07-17 Power-factor detection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9123179A JPS5614955A (en) 1979-07-17 1979-07-17 Power-factor detection circuit

Publications (1)

Publication Number Publication Date
JPS5614955A true JPS5614955A (en) 1981-02-13

Family

ID=14020640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9123179A Pending JPS5614955A (en) 1979-07-17 1979-07-17 Power-factor detection circuit

Country Status (1)

Country Link
JP (1) JPS5614955A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205403A (en) * 1983-05-07 1984-11-21 Sumitomo Electric Ind Ltd Plasma sintering apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59205403A (en) * 1983-05-07 1984-11-21 Sumitomo Electric Ind Ltd Plasma sintering apparatus

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