JPS5616202A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS5616202A
JPS5616202A JP8981679A JP8981679A JPS5616202A JP S5616202 A JPS5616202 A JP S5616202A JP 8981679 A JP8981679 A JP 8981679A JP 8981679 A JP8981679 A JP 8981679A JP S5616202 A JPS5616202 A JP S5616202A
Authority
JP
Japan
Prior art keywords
memory
cpu24
cpu22
data input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8981679A
Other languages
Japanese (ja)
Inventor
Naoaki Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8981679A priority Critical patent/JPS5616202A/en
Publication of JPS5616202A publication Critical patent/JPS5616202A/en
Pending legal-status Critical Current

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  • Feedback Control In General (AREA)

Abstract

PURPOSE: To simplify the hardware constitution and to increase the reliability, by providing the main operation control section and memory section for backup, duplicating the memory as well as CPU, and performing the signal switching only between CPU and I/O.
CONSTITUTION: The memory 21 is normally used for the operation of the programmable control unit PC and constitutes the main components with CPU22. On the other hand, the memory 23 is used for backup at main side failure together with CPU24. Further, normally, CPU22 is connected to I/O 25, enabling the data input and output from CPU22 freely. At the same time, CPU24 is connected to I/O 25 so that the data input from I/O 25 is possible for CPU24 but no output request is possible. But, a failure is detected in the failure detection circuit 27 for CPU22 and memory 21, the data input and output of I/O 25 is allowed only to CPU24. Thus, the hardware constitution is made simple to increase the reliability.
COPYRIGHT: (C)1981,JPO&Japio
JP8981679A 1979-07-17 1979-07-17 Programmable controller Pending JPS5616202A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8981679A JPS5616202A (en) 1979-07-17 1979-07-17 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8981679A JPS5616202A (en) 1979-07-17 1979-07-17 Programmable controller

Publications (1)

Publication Number Publication Date
JPS5616202A true JPS5616202A (en) 1981-02-17

Family

ID=13981259

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8981679A Pending JPS5616202A (en) 1979-07-17 1979-07-17 Programmable controller

Country Status (1)

Country Link
JP (1) JPS5616202A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016168986A (en) * 2015-03-16 2016-09-23 日立建機株式会社 Control controller, steer-by-wire system and machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016168986A (en) * 2015-03-16 2016-09-23 日立建機株式会社 Control controller, steer-by-wire system and machine

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