JPS5636727A - Information transfer system - Google Patents

Information transfer system

Info

Publication number
JPS5636727A
JPS5636727A JP11136279A JP11136279A JPS5636727A JP S5636727 A JPS5636727 A JP S5636727A JP 11136279 A JP11136279 A JP 11136279A JP 11136279 A JP11136279 A JP 11136279A JP S5636727 A JPS5636727 A JP S5636727A
Authority
JP
Japan
Prior art keywords
port
priority
ports
request
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11136279A
Other languages
Japanese (ja)
Other versions
JPS6336020B2 (en
Inventor
Naoya Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11136279A priority Critical patent/JPS5636727A/en
Publication of JPS5636727A publication Critical patent/JPS5636727A/en
Publication of JPS6336020B2 publication Critical patent/JPS6336020B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)

Abstract

PURPOSE: To increase the speed of processing by giving higher priority to urgent transfer and lower priority to the other transfer.
CONSTITUTION: Main memory unit 1 has eight access request ports P0WP7. Then, P0 has the top priority and to this port, a memory access request is supplied from I/O device 6 having a high-speed transfer speed such as a magnetic disk. An access request from CPU3 is supplied to the 3rd port P5 from the lowest rank. Further, BORAM unit 2 has request line 11 with higher priority and request line 12 with lower priority; request line 11 is connected to port P3, and request line 12 to port P7. Access requests, applied to ports P0WP7 of main memory unit 1, are inputted to the priority deciding circuit in control circuit 15 of main memory unit 1 and acceptance signals are applied to acceptance signal lines that correspond to the ports having sent those requests.
COPYRIGHT: (C)1981,JPO&Japio
JP11136279A 1979-08-31 1979-08-31 Information transfer system Granted JPS5636727A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11136279A JPS5636727A (en) 1979-08-31 1979-08-31 Information transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11136279A JPS5636727A (en) 1979-08-31 1979-08-31 Information transfer system

Publications (2)

Publication Number Publication Date
JPS5636727A true JPS5636727A (en) 1981-04-10
JPS6336020B2 JPS6336020B2 (en) 1988-07-18

Family

ID=14559264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11136279A Granted JPS5636727A (en) 1979-08-31 1979-08-31 Information transfer system

Country Status (1)

Country Link
JP (1) JPS5636727A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0752467B2 (en) * 1987-11-16 1995-06-05 インテル コーポレーシヨン Video signal processing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414133A (en) * 1977-07-05 1979-02-02 Mitsubishi Electric Corp Control system for input and output channel

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5414133A (en) * 1977-07-05 1979-02-02 Mitsubishi Electric Corp Control system for input and output channel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0752467B2 (en) * 1987-11-16 1995-06-05 インテル コーポレーシヨン Video signal processing system

Also Published As

Publication number Publication date
JPS6336020B2 (en) 1988-07-18

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