JPS5642830A - Priority interruption control system for data processor - Google Patents

Priority interruption control system for data processor

Info

Publication number
JPS5642830A
JPS5642830A JP11985179A JP11985179A JPS5642830A JP S5642830 A JPS5642830 A JP S5642830A JP 11985179 A JP11985179 A JP 11985179A JP 11985179 A JP11985179 A JP 11985179A JP S5642830 A JPS5642830 A JP S5642830A
Authority
JP
Japan
Prior art keywords
interruption
unit
peripheral unit
control system
serial connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11985179A
Other languages
Japanese (ja)
Inventor
Teiji Nishizawa
Katsura Kawakami
Sumio Ozawa
Masashi Deguchi
Hiroshi Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11985179A priority Critical patent/JPS5642830A/en
Publication of JPS5642830A publication Critical patent/JPS5642830A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To realize a multiplex interruption for the priority interruption control system between the peripheral unit and the CPU, not only by securing a serial connection for each peripheral unit via the normal interruption answer signal line but by securing a serial connection for each peripheral unit via the interruption request line.
CONSTITUTION: When an interruption request is produced at an optional peripheral unit 21, the interruption request signal IRQ' is supplied to the CPU1 after passing through the higher-rank peripheral unit 20 directly. The answer signal IAK is sent to the unit 21 after passing through the unit 20 directly. And the transmission of the signal IAK is cut off within the unit 21, and the interruption data word generated according to the transmission cutoff of the signal IAK is sent to the CPU1 via the system bus 5. Thus a serial connection is secured between the units 21 and 20 by the IRQ', at the same time realizing a multiplex interruption.
COPYRIGHT: (C)1981,JPO&Japio
JP11985179A 1979-09-18 1979-09-18 Priority interruption control system for data processor Pending JPS5642830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11985179A JPS5642830A (en) 1979-09-18 1979-09-18 Priority interruption control system for data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11985179A JPS5642830A (en) 1979-09-18 1979-09-18 Priority interruption control system for data processor

Publications (1)

Publication Number Publication Date
JPS5642830A true JPS5642830A (en) 1981-04-21

Family

ID=14771833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11985179A Pending JPS5642830A (en) 1979-09-18 1979-09-18 Priority interruption control system for data processor

Country Status (1)

Country Link
JP (1) JPS5642830A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176439A (en) * 1981-04-24 1982-10-29 Hitachi Ltd Service request transmission control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57176439A (en) * 1981-04-24 1982-10-29 Hitachi Ltd Service request transmission control system

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