JPS564839A - Operating method for software - Google Patents

Operating method for software

Info

Publication number
JPS564839A
JPS564839A JP7881279A JP7881279A JPS564839A JP S564839 A JPS564839 A JP S564839A JP 7881279 A JP7881279 A JP 7881279A JP 7881279 A JP7881279 A JP 7881279A JP S564839 A JPS564839 A JP S564839A
Authority
JP
Japan
Prior art keywords
shift
multiplication
bits
division
constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7881279A
Other languages
Japanese (ja)
Inventor
Akihiko Maekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7881279A priority Critical patent/JPS564839A/en
Publication of JPS564839A publication Critical patent/JPS564839A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To remarkably reduce the processing time, by replacing the multiplication and division into the shift processing of bits using shift registers.
CONSTITUTION: When the content of the shift register R storing the data of "00001000" in binary number is shifted left by n bits, it is equivalent as the multiplication of "×2n" and when shifted right by n bits, it is equal as the division of "÷2n". Thus, the multiplication and division can be replaced into the bit processing using shift registers. For example, A×10=(A×23)+(A×21) is obtained. First, the constant A is read out, next, the first term is operated with 3-bit shift left for the constant A, the second term is operated with the constant A shift left by one bit, and the result of the operations is summed.
COPYRIGHT: (C)1981,JPO&Japio
JP7881279A 1979-06-21 1979-06-21 Operating method for software Pending JPS564839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7881279A JPS564839A (en) 1979-06-21 1979-06-21 Operating method for software

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7881279A JPS564839A (en) 1979-06-21 1979-06-21 Operating method for software

Publications (1)

Publication Number Publication Date
JPS564839A true JPS564839A (en) 1981-01-19

Family

ID=13672248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7881279A Pending JPS564839A (en) 1979-06-21 1979-06-21 Operating method for software

Country Status (1)

Country Link
JP (1) JPS564839A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856593A (en) * 1981-09-12 1983-04-04 エヌ　ベー　フイリップス　フルーイランペンフアブリケン Signal amplitude ratio adjusting circuit
US5771186A (en) * 1995-06-07 1998-06-23 International Business Machines System and method for multiplying in a data processing system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856593A (en) * 1981-09-12 1983-04-04 エヌ　ベー　フイリップス　フルーイランペンフアブリケン Signal amplitude ratio adjusting circuit
US5771186A (en) * 1995-06-07 1998-06-23 International Business Machines System and method for multiplying in a data processing system

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