JPS5654561A - Memory interleaving control system - Google Patents

Memory interleaving control system

Info

Publication number
JPS5654561A
JPS5654561A JP13167879A JP13167879A JPS5654561A JP S5654561 A JPS5654561 A JP S5654561A JP 13167879 A JP13167879 A JP 13167879A JP 13167879 A JP13167879 A JP 13167879A JP S5654561 A JPS5654561 A JP S5654561A
Authority
JP
Japan
Prior art keywords
memory
interleaved bits
unit
decision
cope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13167879A
Other languages
Japanese (ja)
Other versions
JPS5953588B2 (en
Inventor
Haruhiko Tsunoda
Masayuki Okawa
Yuzo Hayashi
Haruo Hayamizu
Hideki Fukuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NTT Inc
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP13167879A priority Critical patent/JPS5953588B2/en
Publication of JPS5654561A publication Critical patent/JPS5654561A/en
Publication of JPS5953588B2 publication Critical patent/JPS5953588B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to cope with extension as a user desires, by supplying a memory actuating circuit with the decision result of an interleaving decision part and interleaved bits and by determining a memory constituent unit to be accessed.
CONSTITUTION: Address number comparison part 6 compares memory-constituting- unit corresponding bits in access address information, generated by access request device 3, with address number information. Then, interleaving decision part 7 decides the number of interleaved bits supplied by memories by interleaved bits and package/nonpackage discrimination flags in the access address information. The decision result of this decision part 7 and interleaved bits are supplied to memory actuating circuit 8 to determine the memory constituting unit to be accessed. Consequently, it is made possible to cope with the modification of the constitution of the memory unit freely and extension can also be coped with the desire of users.
COPYRIGHT: (C)1981,JPO&Japio
JP13167879A 1979-10-12 1979-10-12 Memory interleave control method Expired JPS5953588B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13167879A JPS5953588B2 (en) 1979-10-12 1979-10-12 Memory interleave control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13167879A JPS5953588B2 (en) 1979-10-12 1979-10-12 Memory interleave control method

Publications (2)

Publication Number Publication Date
JPS5654561A true JPS5654561A (en) 1981-05-14
JPS5953588B2 JPS5953588B2 (en) 1984-12-26

Family

ID=15063659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13167879A Expired JPS5953588B2 (en) 1979-10-12 1979-10-12 Memory interleave control method

Country Status (1)

Country Link
JP (1) JPS5953588B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400293A (en) * 1992-11-10 1995-03-21 Oki Electric Industry Co., Ltd. Method of setting addresses of memories

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6126968A (en) * 1984-07-18 1986-02-06 Mitsubishi Electric Corp Disk clamping device
JP6655743B1 (en) 2019-03-27 2020-02-26 悟朗 西本 User development support system, user development support method, and user development support program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5400293A (en) * 1992-11-10 1995-03-21 Oki Electric Industry Co., Ltd. Method of setting addresses of memories

Also Published As

Publication number Publication date
JPS5953588B2 (en) 1984-12-26

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