JPS5656647A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5656647A
JPS5656647A JP13325179A JP13325179A JPS5656647A JP S5656647 A JPS5656647 A JP S5656647A JP 13325179 A JP13325179 A JP 13325179A JP 13325179 A JP13325179 A JP 13325179A JP S5656647 A JPS5656647 A JP S5656647A
Authority
JP
Japan
Prior art keywords
layer
island
porous
anodizing
integrity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13325179A
Other languages
Japanese (ja)
Other versions
JPS5951745B2 (en
Inventor
Seiji Onaka
Kosei Kajiwara
Tatsunori Nakajima
Kazutoshi Nagano
Kosuke Yasuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54133251A priority Critical patent/JPS5951745B2/en
Publication of JPS5656647A publication Critical patent/JPS5656647A/en
Publication of JPS5951745B2 publication Critical patent/JPS5951745B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/191—Preparing SOI wafers using full isolation by porous oxide silicon [FIPOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain the device high in both performance and integrity by a method wherein an N+ layer is provided in a desired region of an N type substrate, an N tupe island surrounded by P layer is formed thereon, the P layer is made porous through anodizing and further insulated to isolate the island. CONSTITUTION:The N<+> layer 11 is formed in a desired region of an N type substrate 10 by implanting ion selectively at high density. A P epitaxial layer 12 and an N epitaxial layer 13 are laminated thereon, an opening 15 is provided in an SiO2 film 14 to diffusion, and a P layer 16 is connected to the P layer 12 to form an N type island 17. Next, only the P layers 12, 16 are made to a porous Si 18 through anodizing in electrolyte. The substrate 10 is not made porous inside of the N<+> layer 11. Then, the layer 18 becomes SiO2 layer 19 when subjected to heat treatment in an oxidative atmosphere. The porous layer 18 at F part of the island 17 is uniform in thickness and thus no strain will be brought on the island at the time of oxidation of the layer 18, therefore noises will not arise due to deterioration or defect in mobility of a carrier, and the surface of the island becomes flat, which is ready for fine working. A high performance and integrity of a device is thus obtainable.
JP54133251A 1979-10-15 1979-10-15 Manufacturing method of semiconductor device Expired JPS5951745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54133251A JPS5951745B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54133251A JPS5951745B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5656647A true JPS5656647A (en) 1981-05-18
JPS5951745B2 JPS5951745B2 (en) 1984-12-15

Family

ID=15100233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54133251A Expired JPS5951745B2 (en) 1979-10-15 1979-10-15 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5951745B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575879A (en) * 2015-12-17 2016-05-11 上海集成电路研发中心有限公司 Forming method of totally-isolated active region structure
CN105590892A (en) * 2015-12-17 2016-05-18 上海集成电路研发中心有限公司 Method for preparing full-isolated active region structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51278A (en) * 1974-06-18 1976-01-05 Matsushita Electric Industrial Co Ltd Handotaishusekikairokitaino seizohoho
JPS5357979A (en) * 1976-11-06 1978-05-25 Matsushita Electric Ind Co Ltd Semiconductor device and its production

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51278A (en) * 1974-06-18 1976-01-05 Matsushita Electric Industrial Co Ltd Handotaishusekikairokitaino seizohoho
JPS5357979A (en) * 1976-11-06 1978-05-25 Matsushita Electric Ind Co Ltd Semiconductor device and its production

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105575879A (en) * 2015-12-17 2016-05-11 上海集成电路研发中心有限公司 Forming method of totally-isolated active region structure
CN105590892A (en) * 2015-12-17 2016-05-18 上海集成电路研发中心有限公司 Method for preparing full-isolated active region structure

Also Published As

Publication number Publication date
JPS5951745B2 (en) 1984-12-15

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