JPS5657143A - Microprogram storage device - Google Patents

Microprogram storage device

Info

Publication number
JPS5657143A
JPS5657143A JP13312779A JP13312779A JPS5657143A JP S5657143 A JPS5657143 A JP S5657143A JP 13312779 A JP13312779 A JP 13312779A JP 13312779 A JP13312779 A JP 13312779A JP S5657143 A JPS5657143 A JP S5657143A
Authority
JP
Japan
Prior art keywords
ram
circuit
address
rom
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13312779A
Other languages
Japanese (ja)
Inventor
Tsukasa Furuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13312779A priority Critical patent/JPS5657143A/en
Publication of JPS5657143A publication Critical patent/JPS5657143A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate correction of a microprogram, by providing an ROM, a RAM, and a means which transfers the microprogram from the ROM to the RAM and corrects it.
CONSTITUTION: In case of transfer of micro instructions, AND-OR circuit 4 selects transfer address 204 output from address counter circuit 3. Address 205 selected by circuit 4 is given to ROM 1 and RAM 2. Micro instruction 202 read out from ROM 1 is written into RAM 2 through AND-OR circuit 5. In case of correction of micro instructions, switch circuit 7 is operated to set address switch 701 to the address of the micro instruction, and the micro instruction is set by micro instruction switch 702. Circuit 5 selects corrections data from switch 702 and writes it into RAM 2. For execution of micro instructions, in case of the use of RAM 2, address 205 selected by circuit 4 is supplied to RAM 2, and micro instruction 208 is read out from RAM 2 and is output through AND-OR circuit 6.
COPYRIGHT: (C)1981,JPO&Japio
JP13312779A 1979-10-16 1979-10-16 Microprogram storage device Pending JPS5657143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13312779A JPS5657143A (en) 1979-10-16 1979-10-16 Microprogram storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13312779A JPS5657143A (en) 1979-10-16 1979-10-16 Microprogram storage device

Publications (1)

Publication Number Publication Date
JPS5657143A true JPS5657143A (en) 1981-05-19

Family

ID=15097407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13312779A Pending JPS5657143A (en) 1979-10-16 1979-10-16 Microprogram storage device

Country Status (1)

Country Link
JP (1) JPS5657143A (en)

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