JPS5659331A - Logical device - Google Patents

Logical device

Info

Publication number
JPS5659331A
JPS5659331A JP13564879A JP13564879A JPS5659331A JP S5659331 A JPS5659331 A JP S5659331A JP 13564879 A JP13564879 A JP 13564879A JP 13564879 A JP13564879 A JP 13564879A JP S5659331 A JPS5659331 A JP S5659331A
Authority
JP
Japan
Prior art keywords
clock
phase
generator
controlling
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13564879A
Other languages
Japanese (ja)
Inventor
Yamato Masumoto
Mikiya Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13564879A priority Critical patent/JPS5659331A/en
Publication of JPS5659331A publication Critical patent/JPS5659331A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To get rid of an error due to the secular change, by detecting the phase shift of other clock through basing on one output of a generator which generates a number of clocks, and controlling the generator.
CONSTITUTION: A clock which has been taken out from the logical blocks 104, 105 is transmitted to the phase difference detection circuit 113, 114, and the phase is compared with that of a reference clock from the logical block 106. The output of the phase difference detection circuits 113, 114 is input to the control input of the delay control circuits 102, 103, and a phase error of the clock from the logical blocks 104, 105 is corrected by controlling the phase of the outputs 152, 153 from the clock generating circuit 101.
COPYRIGHT: (C)1981,JPO&Japio
JP13564879A 1979-10-19 1979-10-19 Logical device Pending JPS5659331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13564879A JPS5659331A (en) 1979-10-19 1979-10-19 Logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13564879A JPS5659331A (en) 1979-10-19 1979-10-19 Logical device

Publications (1)

Publication Number Publication Date
JPS5659331A true JPS5659331A (en) 1981-05-22

Family

ID=15156703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13564879A Pending JPS5659331A (en) 1979-10-19 1979-10-19 Logical device

Country Status (1)

Country Link
JP (1) JPS5659331A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63231516A (en) * 1987-03-20 1988-09-27 Hitachi Ltd Clock signal supply device
JPH04346111A (en) * 1991-05-23 1992-12-02 Nec Corp Integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63231516A (en) * 1987-03-20 1988-09-27 Hitachi Ltd Clock signal supply device
JPH04346111A (en) * 1991-05-23 1992-12-02 Nec Corp Integrated circuit

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