JPS5660930A - Data transfer system - Google Patents

Data transfer system

Info

Publication number
JPS5660930A
JPS5660930A JP13728579A JP13728579A JPS5660930A JP S5660930 A JPS5660930 A JP S5660930A JP 13728579 A JP13728579 A JP 13728579A JP 13728579 A JP13728579 A JP 13728579A JP S5660930 A JPS5660930 A JP S5660930A
Authority
JP
Japan
Prior art keywords
address
buffer
signal
cpu1
identity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13728579A
Other languages
Japanese (ja)
Inventor
Noritaka Nakano
Kyoji Kameo
Takao Sakata
Takao Sagane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
KDDI Corp
Original Assignee
Fujitsu Ltd
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Kokusai Denshin Denwa KK filed Critical Fujitsu Ltd
Priority to JP13728579A priority Critical patent/JPS5660930A/en
Publication of JPS5660930A publication Critical patent/JPS5660930A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To provide the system with flexibility and extensibility by simplifying address signals by collating an address signal on an address bus with the contents of a buffer by a matching circuit and by applying an interruption signal to a tributary processor when their identity is found.
CONSTITUTION: In low-speed CPU, for example, tributary processor CPU1, address information stored in RAM1 is previously transferred to buffer BF1 and matching circuit MAT1 collates an address signal on address bus AB with the contents of buffer BF1. When their identity is found, interruption signal IRQ is applied to tributary processor CPU1. In response to interruption signal IRQ, this CPU1 interrupts processing such as start-stop regeneration temporarily, trasfers low-speed data to multiple conversion unit MCU via data bus DB, and also read and transfers the next address information from memory RAM1 to buffer BF1. Thus, the address signal is simplified to facilitate a supervision on the buses, so that the system may be flexible and extensible.
COPYRIGHT: (C)1981,JPO&Japio
JP13728579A 1979-10-24 1979-10-24 Data transfer system Pending JPS5660930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13728579A JPS5660930A (en) 1979-10-24 1979-10-24 Data transfer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13728579A JPS5660930A (en) 1979-10-24 1979-10-24 Data transfer system

Publications (1)

Publication Number Publication Date
JPS5660930A true JPS5660930A (en) 1981-05-26

Family

ID=15195102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13728579A Pending JPS5660930A (en) 1979-10-24 1979-10-24 Data transfer system

Country Status (1)

Country Link
JP (1) JPS5660930A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123148A (en) * 1982-01-18 1983-07-22 Hitachi Ltd Data transmitting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58123148A (en) * 1982-01-18 1983-07-22 Hitachi Ltd Data transmitting system

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