JPS5665251A - Instruction reexecution system - Google Patents

Instruction reexecution system

Info

Publication number
JPS5665251A
JPS5665251A JP14134179A JP14134179A JPS5665251A JP S5665251 A JPS5665251 A JP S5665251A JP 14134179 A JP14134179 A JP 14134179A JP 14134179 A JP14134179 A JP 14134179A JP S5665251 A JPS5665251 A JP S5665251A
Authority
JP
Japan
Prior art keywords
instruction
register
execution
processing unit
reexecution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14134179A
Other languages
Japanese (ja)
Inventor
Minoru Nishisaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14134179A priority Critical patent/JPS5665251A/en
Publication of JPS5665251A publication Critical patent/JPS5665251A/en
Pending legal-status Critical Current

Links

Landscapes

  • Retry When Errors Occur (AREA)

Abstract

PURPOSE: To guarantee the covery operation and elevate the reliability of a data processing unit without deteriorating the performance in the course of execution of the firmware instruction, by dividing the firmware instruction into modules.
CONSTITUTION: An instruction code is set to the control memory register CSR2 by reading out the microinstruction for indicating the start of execution of the instruction stored in the control memory CS1. A register code of this register 2 is selected by the register decoder DEC3, and it is provided to the AND gates 13, 14. The timings TP1, TR2 generated by processing unit are provided to said gates 13, 14, the logical product with an output of the decoder 3 is taken, and a signal for indicating the write operation of the address register 6 and the program counter 8, plus a signal for resetting the retry control FF9 which controls the reexecution of the instruction are output. And the software program instruction sequence by the processing unit is controlled by the counter 8 so that the covery operation can be executed without deteriorating the performance in the cource of execution of the firmware instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP14134179A 1979-11-02 1979-11-02 Instruction reexecution system Pending JPS5665251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14134179A JPS5665251A (en) 1979-11-02 1979-11-02 Instruction reexecution system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14134179A JPS5665251A (en) 1979-11-02 1979-11-02 Instruction reexecution system

Publications (1)

Publication Number Publication Date
JPS5665251A true JPS5665251A (en) 1981-06-02

Family

ID=15289699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14134179A Pending JPS5665251A (en) 1979-11-02 1979-11-02 Instruction reexecution system

Country Status (1)

Country Link
JP (1) JPS5665251A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979650A (en) * 1972-12-07 1974-08-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4979650A (en) * 1972-12-07 1974-08-01

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