JPS5668836A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5668836A
JPS5668836A JP14510079A JP14510079A JPS5668836A JP S5668836 A JPS5668836 A JP S5668836A JP 14510079 A JP14510079 A JP 14510079A JP 14510079 A JP14510079 A JP 14510079A JP S5668836 A JPS5668836 A JP S5668836A
Authority
JP
Japan
Prior art keywords
error
error occurrence
information memory
loader
mem
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14510079A
Other languages
Japanese (ja)
Inventor
Toshiyuki Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14510079A priority Critical patent/JPS5668836A/en
Publication of JPS5668836A publication Critical patent/JPS5668836A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To facilitate an easy writing and reading for the error occurrence information, by giving a control so that the contents of the error occurrence information memory device may be shifted to the error information memory area which is set previously within a loader.
CONSTITUTION: When the microprogram reading device MPG reads the program out of the control storage CST, the correction working circuit EBC performs the detection and correction for the 1-bit error. The circuit EBC sends out one unit of pulse to the counter CNT with every correction and at the same time sends the position information of the error occurrence bit to the error occurrence information memory device MEM. When the device MEM counts the prescribed frequency of the 1-bit errors, the device MEM becomes full. Then the counter CNT produces the overflow signal OFS. As a result, the loader control circuit LCT gives a control so that the contents of the MEM may be shifted to the error information memory area which is set previously within the loader LDR. As a result, both the writing and reading can be facilitated for the error occurrence information.
COPYRIGHT: (C)1981,JPO&Japio
JP14510079A 1979-11-09 1979-11-09 Microprogram control unit Pending JPS5668836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14510079A JPS5668836A (en) 1979-11-09 1979-11-09 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14510079A JPS5668836A (en) 1979-11-09 1979-11-09 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5668836A true JPS5668836A (en) 1981-06-09

Family

ID=15377365

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14510079A Pending JPS5668836A (en) 1979-11-09 1979-11-09 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5668836A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081036A (en) * 1973-11-15 1975-07-01
JPS53140940A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Memory circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5081036A (en) * 1973-11-15 1975-07-01
JPS53140940A (en) * 1977-05-16 1978-12-08 Hitachi Ltd Memory circuit

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