JPS567143A - Data converting circuit - Google Patents

Data converting circuit

Info

Publication number
JPS567143A
JPS567143A JP8190579A JP8190579A JPS567143A JP S567143 A JPS567143 A JP S567143A JP 8190579 A JP8190579 A JP 8190579A JP 8190579 A JP8190579 A JP 8190579A JP S567143 A JPS567143 A JP S567143A
Authority
JP
Japan
Prior art keywords
circuit
address
conversion information
data
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8190579A
Other languages
Japanese (ja)
Inventor
Susumu Kojima
Masao Murai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8190579A priority Critical patent/JPS567143A/en
Publication of JPS567143A publication Critical patent/JPS567143A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To reduce greatly the time required for the conversion process such as the bit operation and the like, by forming the conversion information set to the memory circuit in such way that the information may be read out automatically with advance of the address of the conversion information secured by the counter circuit.
CONSTITUTION: The address-to-memory contents' conversion information is set previously to conversion information memory circuit 5; and at the same time the compressed data equivelent to one test clock is set previously to data memory circuit 7 from address 0 and so on. When the start order for the conversion process is given from control unit 1, gate 3 opens to supply clock pulse CP to counter circuit 4 from terminal 14. And then one bit of the data in the address equal to the contents of address 0 in circuit 5 is delivered from circuit 7. For this one bit of data, the 1st CP is supplied to circuit 4 and also taken into m-bit shift register 9. After this, the CP is supplied in sequence to circuit 4, and the address of the conversion information in ciricuit 5 in advanced to repeat the same action as above. And when the output of circuit 4 becomes m-1, gate 3 is closed to the CP via gate signal compounding circuit 2.
COPYRIGHT: (C)1981,JPO&Japio
JP8190579A 1979-06-28 1979-06-28 Data converting circuit Pending JPS567143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8190579A JPS567143A (en) 1979-06-28 1979-06-28 Data converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8190579A JPS567143A (en) 1979-06-28 1979-06-28 Data converting circuit

Publications (1)

Publication Number Publication Date
JPS567143A true JPS567143A (en) 1981-01-24

Family

ID=13759451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8190579A Pending JPS567143A (en) 1979-06-28 1979-06-28 Data converting circuit

Country Status (1)

Country Link
JP (1) JPS567143A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS597857A (en) * 1982-07-02 1984-01-17 ダイキン工業株式会社 Heat pump type air conditioner
JPS61165092U (en) * 1985-03-29 1986-10-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS597857A (en) * 1982-07-02 1984-01-17 ダイキン工業株式会社 Heat pump type air conditioner
JPS61165092U (en) * 1985-03-29 1986-10-13

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