JPS567158A - Load state display unit fr multiload control system - Google Patents

Load state display unit fr multiload control system

Info

Publication number
JPS567158A
JPS567158A JP8291779A JP8291779A JPS567158A JP S567158 A JPS567158 A JP S567158A JP 8291779 A JP8291779 A JP 8291779A JP 8291779 A JP8291779 A JP 8291779A JP S567158 A JPS567158 A JP S567158A
Authority
JP
Japan
Prior art keywords
memory
switch
load state
cpu1
state display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8291779A
Other languages
Japanese (ja)
Inventor
Yoshiharu Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP8291779A priority Critical patent/JPS567158A/en
Publication of JPS567158A publication Critical patent/JPS567158A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Selective Calling Equipment (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To reduce the memory data transfer time of the CPU, by providing the change-over switch to the input of the load state display part and then connecting one switch input end to the memory which storing the load state.
CONSTITUTION: In the system which gives the individual control to a number of loads from microprocessor CPU1 and in the time-division multiple transmission system, memory 3 which stores the state of each load is connected to input common bus 2 of CPU1. At the same time, change-over switch 6 is provided to the input side of load state display part 5 where the states of many loads are displayed. Switch input end (a) of switch 6 is connected to output common bus 4 of CPU1; and switch input end (b) is connected to the output end of memory 3 each. When switch 6 is turned to end (b), the read address signal and the latch signal are supplied to memory 3 and part 5 each from CPU1. As a result, the data given from memory 3 is supplied directly to part 5 to accelerate the response time of the CPU. Thus the display process working time can be reduced per channel.
COPYRIGHT: (C)1981,JPO&Japio
JP8291779A 1979-06-30 1979-06-30 Load state display unit fr multiload control system Pending JPS567158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8291779A JPS567158A (en) 1979-06-30 1979-06-30 Load state display unit fr multiload control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8291779A JPS567158A (en) 1979-06-30 1979-06-30 Load state display unit fr multiload control system

Publications (1)

Publication Number Publication Date
JPS567158A true JPS567158A (en) 1981-01-24

Family

ID=13787592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8291779A Pending JPS567158A (en) 1979-06-30 1979-06-30 Load state display unit fr multiload control system

Country Status (1)

Country Link
JP (1) JPS567158A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200985U (en) * 1987-06-17 1988-12-23

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63200985U (en) * 1987-06-17 1988-12-23

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