JPS567281A - Monitor unit - Google Patents

Monitor unit

Info

Publication number
JPS567281A
JPS567281A JP8191579A JP8191579A JPS567281A JP S567281 A JPS567281 A JP S567281A JP 8191579 A JP8191579 A JP 8191579A JP 8191579 A JP8191579 A JP 8191579A JP S567281 A JPS567281 A JP S567281A
Authority
JP
Japan
Prior art keywords
value
unit
monitor
interrupt
sets
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8191579A
Other languages
Japanese (ja)
Inventor
Noritaka Umeno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8191579A priority Critical patent/JPS567281A/en
Publication of JPS567281A publication Critical patent/JPS567281A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To reduce overhead of monitor and prevent needless interrupt, by interrupting the system to change succeeding monitor conditions when the output of a measuring unit which generates within a fixed period reaches a fixed condition.
CONSTITUTION: When the value of mode F/F 14 becomes "0", monitor unit 1 monitors whether the value of counter 11 is equal to or larger than the value of register (upper limit value) or not according to the instruction of timing circuit 15, and monitor unit 1 sets the value of output signal 118 and the value of F/F 14 to "1" when this condition is satisfied, and thus, the interrupt signal to the CPU of information processing system 3 is generated. After that, unit 1 monitors whether the value of counter 11 is equal to or smaller than the value of register 13 (lower limit value) or not according to the instruction of circuit 15, and unit 1 sets the value of output signal 118 to "1" to interrupt the CPU of system 3 when this condition is satisfied, and unit 1 sets the value of F/F 14 to "0", and similar operations are repeated. As a result, overhead of monitor can be reduced, and the continuous interrupt of the same matter and so on can be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP8191579A 1979-06-28 1979-06-28 Monitor unit Pending JPS567281A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8191579A JPS567281A (en) 1979-06-28 1979-06-28 Monitor unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8191579A JPS567281A (en) 1979-06-28 1979-06-28 Monitor unit

Publications (1)

Publication Number Publication Date
JPS567281A true JPS567281A (en) 1981-01-24

Family

ID=13759739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8191579A Pending JPS567281A (en) 1979-06-28 1979-06-28 Monitor unit

Country Status (1)

Country Link
JP (1) JPS567281A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153355A (en) * 1981-03-18 1982-09-21 Fujitsu Ltd Storage device control system
JPH0354480U (en) * 1989-09-26 1991-05-27

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57153355A (en) * 1981-03-18 1982-09-21 Fujitsu Ltd Storage device control system
JPH0354480U (en) * 1989-09-26 1991-05-27

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