JPS5676820A - Memory control unit - Google Patents
Memory control unitInfo
- Publication number
- JPS5676820A JPS5676820A JP15485179A JP15485179A JPS5676820A JP S5676820 A JPS5676820 A JP S5676820A JP 15485179 A JP15485179 A JP 15485179A JP 15485179 A JP15485179 A JP 15485179A JP S5676820 A JPS5676820 A JP S5676820A
- Authority
- JP
- Japan
- Prior art keywords
- ram
- signal
- cpu
- breakdown
- slope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000007257 malfunction Effects 0.000 abstract 2
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Direct Current Feeding And Distribution (AREA)
- Power Sources (AREA)
Abstract
PURPOSE: To avoid the breakdown of the memory information caused by the malfunction during the unsteady operation of the CPU, by detecting the slope of the main power source having the slow rise and fall and then using this detected signal for the control signal.
CONSTITUTION: The address terminals A0WA9 plus the data terminals D0WD3 of the CPU are connected to the RAM, and the data is stored into the RAM. The CMOSGATE which gates the output given from the Schmitt trigger circuit ST as well as the mode signal/write signal SR/W is connected to the RAM, and the signal is supplied to the R/W terminal of the RAM from the GATE. Then the trigger circuit ST detects the slope of the main power source having the slow rise and fall of the output VMP, and the signal detected by the circuit ST is applied to the GATE in the form of the control signal. Then the R/W terminal is set forcubly at H level, thus preventing the breakdown of the memory information of the RAM which is caused by the malfunction during the unsteady period of the CPU.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15485179A JPS5676820A (en) | 1979-11-28 | 1979-11-28 | Memory control unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15485179A JPS5676820A (en) | 1979-11-28 | 1979-11-28 | Memory control unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5676820A true JPS5676820A (en) | 1981-06-24 |
Family
ID=15593282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15485179A Pending JPS5676820A (en) | 1979-11-28 | 1979-11-28 | Memory control unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5676820A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170846A (en) * | 1985-01-25 | 1986-08-01 | Oki Electric Ind Co Ltd | Store protecting circuit of memory element |
-
1979
- 1979-11-28 JP JP15485179A patent/JPS5676820A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61170846A (en) * | 1985-01-25 | 1986-08-01 | Oki Electric Ind Co Ltd | Store protecting circuit of memory element |
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