JPS5680717A - Actuation control system of arithmetic processor - Google Patents
Actuation control system of arithmetic processorInfo
- Publication number
- JPS5680717A JPS5680717A JP15719279A JP15719279A JPS5680717A JP S5680717 A JPS5680717 A JP S5680717A JP 15719279 A JP15719279 A JP 15719279A JP 15719279 A JP15719279 A JP 15719279A JP S5680717 A JPS5680717 A JP S5680717A
- Authority
- JP
- Japan
- Prior art keywords
- intervals
- signal
- arithmetic processor
- self
- seconds
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 abstract 3
- 238000004092 self-diagnosis Methods 0.000 abstract 3
- 230000007257 malfunction Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Landscapes
- Safety Devices In Control Systems (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To prevent the malfunction and interruption of an arithmetic processor by providing a monitoring circuit that monitors time intervals of a device normalcy signal while permitting the arithmetic processor to make a self-diagnosis of whether arithmetic processing is normally in process or not.
CONSTITUTION: Unless the ambient temperature of arithmetic processor 1 reaches a normal operation temperature after the power source is put to work, device normalcy signal K is not outputted. Monitoring circuit 5 outputs start signal WP at intervals of B seconds with its own one-shot pulse. As a result, the arithmetic processor is repeatedly actuated at intervals of B seconds to make a self-diagnosis according to its self-diagnostic program. As the ambient temperature reaches the normal operation temperature through the operation of heater 2, device normalcy signal K is outputted. Then, the self-diagnosis is carried out at intervals of A seconds during its arithmetic processing execution. Signal K is outputted from bus line 6 at intervals of A seconds and the monitoring circuit is reset at A-second intervals and never outputs signal WP.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54157192A JPS5936281B2 (en) | 1979-12-04 | 1979-12-04 | Processing unit startup control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54157192A JPS5936281B2 (en) | 1979-12-04 | 1979-12-04 | Processing unit startup control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5680717A true JPS5680717A (en) | 1981-07-02 |
| JPS5936281B2 JPS5936281B2 (en) | 1984-09-03 |
Family
ID=15644204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54157192A Expired JPS5936281B2 (en) | 1979-12-04 | 1979-12-04 | Processing unit startup control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5936281B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5884327A (en) * | 1981-11-13 | 1983-05-20 | Hitachi Ltd | Start controlling system of electronic computer system |
| JPS59136824A (en) * | 1983-01-27 | 1984-08-06 | Fujitsu Ltd | Control system of power supply |
-
1979
- 1979-12-04 JP JP54157192A patent/JPS5936281B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5884327A (en) * | 1981-11-13 | 1983-05-20 | Hitachi Ltd | Start controlling system of electronic computer system |
| JPS59136824A (en) * | 1983-01-27 | 1984-08-06 | Fujitsu Ltd | Control system of power supply |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5936281B2 (en) | 1984-09-03 |
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