JPS5680870A - Data processor - Google Patents

Data processor

Info

Publication number
JPS5680870A
JPS5680870A JP15801979A JP15801979A JPS5680870A JP S5680870 A JPS5680870 A JP S5680870A JP 15801979 A JP15801979 A JP 15801979A JP 15801979 A JP15801979 A JP 15801979A JP S5680870 A JPS5680870 A JP S5680870A
Authority
JP
Japan
Prior art keywords
inefficiency
effective
code
bits
effective code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15801979A
Other languages
Japanese (ja)
Inventor
Mamoru Hinai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15801979A priority Critical patent/JPS5680870A/en
Publication of JPS5680870A publication Critical patent/JPS5680870A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To shorten the time required for inefficiency of the entry by adding an effective code of a plurality of bits to an effective bit part of a high-speed address conversion table and carrying out the ineffective processing of the table based upon this code.
CONSTITUTION: In order to make the high-speed address conversion table 2 ineffective by switching the virtual space, when the purging command in accordance with the program is emitted, all 1 detecting circuit 8 refers to the effective code of a plurality of bits added to the effective bit part of the table 2 stored in a current effective code register 7. Then, as long as the respective bits are not all 1, the effective code is advanced step by step through a plus 1 adding circuit 9 and stored in the register 7 again. In this case, only when the circuit 8 detects all 1, the inefficiency taking a long time similar to the initial condition referring to all the columns is carried out. Accordingly, the time required for the inefficiency of the entry is shortened to enhance the processing speed of the data.
COPYRIGHT: (C)1981,JPO&Japio
JP15801979A 1979-12-07 1979-12-07 Data processor Pending JPS5680870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15801979A JPS5680870A (en) 1979-12-07 1979-12-07 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15801979A JPS5680870A (en) 1979-12-07 1979-12-07 Data processor

Publications (1)

Publication Number Publication Date
JPS5680870A true JPS5680870A (en) 1981-07-02

Family

ID=15662486

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15801979A Pending JPS5680870A (en) 1979-12-07 1979-12-07 Data processor

Country Status (1)

Country Link
JP (1) JPS5680870A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05204755A (en) * 1992-01-23 1993-08-13 Nec Corp Memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05204755A (en) * 1992-01-23 1993-08-13 Nec Corp Memory circuit

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