JPS5680873A - Information processing device of multiple virtual memory system - Google Patents

Information processing device of multiple virtual memory system

Info

Publication number
JPS5680873A
JPS5680873A JP15952679A JP15952679A JPS5680873A JP S5680873 A JPS5680873 A JP S5680873A JP 15952679 A JP15952679 A JP 15952679A JP 15952679 A JP15952679 A JP 15952679A JP S5680873 A JPS5680873 A JP S5680873A
Authority
JP
Japan
Prior art keywords
stp
stack
flag
invalid
information processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15952679A
Other languages
Japanese (ja)
Inventor
Tamotsu Noji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15952679A priority Critical patent/JPS5680873A/en
Publication of JPS5680873A publication Critical patent/JPS5680873A/en
Pending legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To prevent an occurrence of toothless state of STP (table pointer word) stack corresponding to a new registering request by judging the range corresponding to unnecessary STP by the existence of flag or an invalid flag to be set in a table pointer word (STP).
CONSTITUTION: The STP which has become invalid by the completion of the program is set to STP register 10 and a search counter 3 is initialized to 0. Then, the counter 3 is successively counted up, STP stacks are successively read out and it is compared with the invalid STP of the register 10 by a comparator 11. The coincidence output of this comparator 11 becomes an invalid flag and the invalid flag 4 is set every stack number corresponding to the stack 1. By this flag 4, the vacant range of the stack 1 corresponding to the unnecessary STP is judged and a new STP is set in the vacant range at the time of a new registering request and STP stack is effectively used without the toothless state.
COPYRIGHT: (C)1981,JPO&Japio
JP15952679A 1979-12-07 1979-12-07 Information processing device of multiple virtual memory system Pending JPS5680873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15952679A JPS5680873A (en) 1979-12-07 1979-12-07 Information processing device of multiple virtual memory system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15952679A JPS5680873A (en) 1979-12-07 1979-12-07 Information processing device of multiple virtual memory system

Publications (1)

Publication Number Publication Date
JPS5680873A true JPS5680873A (en) 1981-07-02

Family

ID=15695688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15952679A Pending JPS5680873A (en) 1979-12-07 1979-12-07 Information processing device of multiple virtual memory system

Country Status (1)

Country Link
JP (1) JPS5680873A (en)

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