JPS5687141A - Microprogram control device - Google Patents

Microprogram control device

Info

Publication number
JPS5687141A
JPS5687141A JP16349979A JP16349979A JPS5687141A JP S5687141 A JPS5687141 A JP S5687141A JP 16349979 A JP16349979 A JP 16349979A JP 16349979 A JP16349979 A JP 16349979A JP S5687141 A JPS5687141 A JP S5687141A
Authority
JP
Japan
Prior art keywords
address
branch
added
stored
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16349979A
Other languages
Japanese (ja)
Inventor
Hisao Takane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP16349979A priority Critical patent/JPS5687141A/en
Publication of JPS5687141A publication Critical patent/JPS5687141A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a simultaneous execution of a conditional branch when the subroutine is changed back to the main routine and thus realize a high-speed performance, by giving the branches to different addresses based on the conditions of the result of operation and others in case a branch is given to the return address which holds an instruction.
CONSTITUTION: The microinstruction containing the branch address is stored in the control memory 1. Then the instruction of the memory 1 is read out by the control register 2 to be supplied to the arithmetic device 12 and the selection circuit 9. Then +1 is added to the address of the circuit 9 through the adder 10, and 1 is added to the address which gives an access to the memory 1 to be stored in the 1st buffer register 5. At the same time, the address in which +N is added to the contents of the address register 11 is stored in the 2nd buffer register 7. The operation result of the device 12 undergoes a test through the test circuit 13, and the selection circuits 8 and 9 are controlled respectively according to the conditions of the operation result. Then the branch address of the microinstruction plus either one of registers 5 and 7 are selected to carry out the conditional branch.
COPYRIGHT: (C)1981,JPO&Japio
JP16349979A 1979-12-18 1979-12-18 Microprogram control device Pending JPS5687141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16349979A JPS5687141A (en) 1979-12-18 1979-12-18 Microprogram control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16349979A JPS5687141A (en) 1979-12-18 1979-12-18 Microprogram control device

Publications (1)

Publication Number Publication Date
JPS5687141A true JPS5687141A (en) 1981-07-15

Family

ID=15775019

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16349979A Pending JPS5687141A (en) 1979-12-18 1979-12-18 Microprogram control device

Country Status (1)

Country Link
JP (1) JPS5687141A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145326A (en) * 1985-12-20 1987-06-29 Toshiba Corp Microprogram control circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62145326A (en) * 1985-12-20 1987-06-29 Toshiba Corp Microprogram control circuit

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