JPS5687293A - Shift register - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware, by performing both the writing and reading at a time with no mutual overlap with use of a register file which can write and read several data at a time. CONSTITUTION:The register file 1 consists of the n-stage register, and the data given from the writing address buses 2 and 3 are written into the register stages of the addresses shown by the writing counters 6 and 7 and at the same time read onto the reading address buses 4 and 5 form the address stages shown by the reading address counters 10 and 11. The counter 6 counts repetitively 0-(n). The count difference among counters is indicated so that an overlap is avoided between the count difference (a) of the counters 6 and 10 and the count difference (c) of the counters 7 an 11. As a result, both shift registers of (a+1) stages and (c+1) stages work at a time for the file 1.