JPS5687343A - Forming method of wiring - Google Patents

Forming method of wiring

Info

Publication number
JPS5687343A
JPS5687343A JP16391779A JP16391779A JPS5687343A JP S5687343 A JPS5687343 A JP S5687343A JP 16391779 A JP16391779 A JP 16391779A JP 16391779 A JP16391779 A JP 16391779A JP S5687343 A JPS5687343 A JP S5687343A
Authority
JP
Japan
Prior art keywords
pattern
resist
resist film
etching
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16391779A
Other languages
English (en)
Inventor
Koji Hirano
Takeshi Nakajima
Toshiro Tsumori
Atsu Touto
Mitsuru Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16391779A priority Critical patent/JPS5687343A/ja
Publication of JPS5687343A publication Critical patent/JPS5687343A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
JP16391779A 1979-12-17 1979-12-17 Forming method of wiring Pending JPS5687343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16391779A JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16391779A JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Publications (1)

Publication Number Publication Date
JPS5687343A true JPS5687343A (en) 1981-07-15

Family

ID=15783272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16391779A Pending JPS5687343A (en) 1979-12-17 1979-12-17 Forming method of wiring

Country Status (1)

Country Link
JP (1) JPS5687343A (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892224A (ja) * 1981-11-27 1983-06-01 Matsushita Electronics Corp パタ−ン形成方法
JPS61263131A (ja) * 1985-05-15 1986-11-21 Nippon Telegr & Teleph Corp <Ntt> 微細パタ−ン化層形成方法
JPS62120046A (ja) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH0518593U (ja) * 1991-08-21 1993-03-09 株式会社トミー 軌道走行玩具

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892224A (ja) * 1981-11-27 1983-06-01 Matsushita Electronics Corp パタ−ン形成方法
JPS61263131A (ja) * 1985-05-15 1986-11-21 Nippon Telegr & Teleph Corp <Ntt> 微細パタ−ン化層形成方法
JPS62120046A (ja) * 1985-11-20 1987-06-01 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH0518593U (ja) * 1991-08-21 1993-03-09 株式会社トミー 軌道走行玩具

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