JPS5688355A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5688355A
JPS5688355A JP16596579A JP16596579A JPS5688355A JP S5688355 A JPS5688355 A JP S5688355A JP 16596579 A JP16596579 A JP 16596579A JP 16596579 A JP16596579 A JP 16596579A JP S5688355 A JPS5688355 A JP S5688355A
Authority
JP
Japan
Prior art keywords
transistor
transistors
gate electrode
memory device
mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16596579A
Other languages
Japanese (ja)
Other versions
JPS6036107B2 (en
Inventor
Kenji Natori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54165965A priority Critical patent/JPS6036107B2/en
Publication of JPS5688355A publication Critical patent/JPS5688355A/en
Publication of JPS6036107B2 publication Critical patent/JPS6036107B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83138—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having different shapes or dimensions of their gate conductors

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To enhance the integrity and the performance of the semiconductor memory device by forming the device of ordinary MOS transistors and MOS transistors having two layer gate electrode. CONSTITUTION:The first MOS transistor Q11 having ordinary configuration and the second MOS transistor Q12 having two-layer gate electrode are formed on the same semiconductor substrate, the source of the tansistor Q11 is connected to the first gate electrode layer of the transistor Q12, and the connector is used as an information memory anode. The first and second bit lines BL1 and BL2 selected by the addresses in column direction are connected to the drains of the transistors Q11 and Q12 respectively, the first and second word lines WL1 and WL2 selected by the addresses in row direction are connected to the first and second gate electrodes of the transistors Q11 and Q12 respectively, and a power source voltage B is connected to the source of the transistor Q12. Thus, the transistor Q12 is conducted or shut off corresponding to the information ''1'' or ''0'', and operated to read as prescribed.
JP54165965A 1979-12-20 1979-12-20 semiconductor storage device Expired JPS6036107B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54165965A JPS6036107B2 (en) 1979-12-20 1979-12-20 semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54165965A JPS6036107B2 (en) 1979-12-20 1979-12-20 semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS5688355A true JPS5688355A (en) 1981-07-17
JPS6036107B2 JPS6036107B2 (en) 1985-08-19

Family

ID=15822368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54165965A Expired JPS6036107B2 (en) 1979-12-20 1979-12-20 semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS6036107B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656607A (en) * 1983-07-21 1987-04-07 Hitachi, Ltd. Electrically erasable programmable RAM
JPH01133357A (en) * 1987-11-18 1989-05-25 Fujitsu Ltd Semiconductor memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656607A (en) * 1983-07-21 1987-04-07 Hitachi, Ltd. Electrically erasable programmable RAM
JPH01133357A (en) * 1987-11-18 1989-05-25 Fujitsu Ltd Semiconductor memory

Also Published As

Publication number Publication date
JPS6036107B2 (en) 1985-08-19

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