JPS5690318A - Bus sequence control system - Google Patents

Bus sequence control system

Info

Publication number
JPS5690318A
JPS5690318A JP16799679A JP16799679A JPS5690318A JP S5690318 A JPS5690318 A JP S5690318A JP 16799679 A JP16799679 A JP 16799679A JP 16799679 A JP16799679 A JP 16799679A JP S5690318 A JPS5690318 A JP S5690318A
Authority
JP
Japan
Prior art keywords
data
address information
common
bus
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16799679A
Other languages
Japanese (ja)
Other versions
JPS5948411B2 (en
Inventor
Shigeru Hashimoto
Yoichi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16799679A priority Critical patent/JPS5948411B2/en
Publication of JPS5690318A publication Critical patent/JPS5690318A/en
Publication of JPS5948411B2 publication Critical patent/JPS5948411B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To reduce the exclusive time of the common bus and elevate the transfer efficiency of information, by sending out the address information prior to the information corresponding to said address information, by the device which has obtained the usage right of the common bus from the bus control part in the main device or the subsidiary device, when the main device is transferring a data to the subsidiary device.
CONSTITUTION: The central processor equipment 1 and plural input/output devices 3 are connected through the common bus (address part) 4' and the common bus (data part) 4", and the usage right of these common buses 4', 4" is controlled by the bus control part 2. On this equipment 1 are provided the output gate circuits 9, 10 which output the address information and data corresponding to the address register 6, the data retister 7 and the registers 6, 7, the circuits 9, 10 are controlled by the output of the signal generating circuit 5, the address information and the data are separated, and they are transferred to the common buses 4', 4". And, when a data is being transferred between the devices 1, 2, the device which has obtained the usage right of the common buses 4', 4" from the control part 2 sends out the address information, prior to the information corresponding to said address information and the exclusive time of the common buses 4', 4" is reduced.
COPYRIGHT: (C)1981,JPO&Japio
JP16799679A 1979-12-24 1979-12-24 Bus sequence control method Expired JPS5948411B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16799679A JPS5948411B2 (en) 1979-12-24 1979-12-24 Bus sequence control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16799679A JPS5948411B2 (en) 1979-12-24 1979-12-24 Bus sequence control method

Publications (2)

Publication Number Publication Date
JPS5690318A true JPS5690318A (en) 1981-07-22
JPS5948411B2 JPS5948411B2 (en) 1984-11-26

Family

ID=15859860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16799679A Expired JPS5948411B2 (en) 1979-12-24 1979-12-24 Bus sequence control method

Country Status (1)

Country Link
JP (1) JPS5948411B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451789B1 (en) * 2001-10-16 2004-10-08 엘지전자 주식회사 Arbitration apparatus and method of processor for resources share

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451789B1 (en) * 2001-10-16 2004-10-08 엘지전자 주식회사 Arbitration apparatus and method of processor for resources share

Also Published As

Publication number Publication date
JPS5948411B2 (en) 1984-11-26

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