JPS5694585A - Memory transistor circuit - Google Patents

Memory transistor circuit

Info

Publication number
JPS5694585A
JPS5694585A JP17073279A JP17073279A JPS5694585A JP S5694585 A JPS5694585 A JP S5694585A JP 17073279 A JP17073279 A JP 17073279A JP 17073279 A JP17073279 A JP 17073279A JP S5694585 A JPS5694585 A JP S5694585A
Authority
JP
Japan
Prior art keywords
readout
transistor
write
memory transistor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17073279A
Other languages
Japanese (ja)
Inventor
Osamu Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17073279A priority Critical patent/JPS5694585A/en
Publication of JPS5694585A publication Critical patent/JPS5694585A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To avoid mis-write-in in memory transistors which are not yet written in, at readout, by connecting a protection transistor to the source of a memory transistor and making this into nonconductive at readout. CONSTITUTION:A protection transistor 18 is connected in series to the source of an FAMOS type memory transistor 12. Further, at write-in, this protection transistor 18 is conducted and at readout, this is made nonconductive, so that no channel current flows to the memory transistor 12 at readout. For example, by using a circuit shown in Figure, in case of write-in, the control line 17 is controlled to make write-in with conducted transistor 18. Further, in case of readout, the control line 17 is controlled, and with the transistor 18 nonconducted, a readout voltage is fed to the 1st node 9 of the memory transistor selected with the address, column address selection gate line 7 and row address selection gate line 11 for readout.
JP17073279A 1979-12-27 1979-12-27 Memory transistor circuit Pending JPS5694585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17073279A JPS5694585A (en) 1979-12-27 1979-12-27 Memory transistor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17073279A JPS5694585A (en) 1979-12-27 1979-12-27 Memory transistor circuit

Publications (1)

Publication Number Publication Date
JPS5694585A true JPS5694585A (en) 1981-07-31

Family

ID=15910355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17073279A Pending JPS5694585A (en) 1979-12-27 1979-12-27 Memory transistor circuit

Country Status (1)

Country Link
JP (1) JPS5694585A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0586473A4 (en) * 1991-05-06 1994-08-03 Lattice Semiconductor Corporation
US5898616A (en) * 1997-05-08 1999-04-27 Oki Electric Industry Co., Ltd. Semiconductor nonvolatile memory and source circuit for this memory
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0586473A4 (en) * 1991-05-06 1994-08-03 Lattice Semiconductor Corporation
US5898616A (en) * 1997-05-08 1999-04-27 Oki Electric Industry Co., Ltd. Semiconductor nonvolatile memory and source circuit for this memory
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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