JPS5694828A - Phase difference detecting circuit - Google Patents
Phase difference detecting circuitInfo
- Publication number
- JPS5694828A JPS5694828A JP17102079A JP17102079A JPS5694828A JP S5694828 A JPS5694828 A JP S5694828A JP 17102079 A JP17102079 A JP 17102079A JP 17102079 A JP17102079 A JP 17102079A JP S5694828 A JPS5694828 A JP S5694828A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- phase difference
- measured
- signals
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
- G01R25/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Measuring Phase Differences (AREA)
Abstract
PURPOSE:To ensure a highly accurate detection for the phase difference, by having a process in which the phase difference between the reference signal and the signal to be measured is once increased double. CONSTITUTION:The reference signal 1 and the signal 2 to be measured are put into the monostable multivibrators 3 and 4 respectively and then branched into two parts after a shaping process to obtain the signals (a)-(d). The signals (b) and (d) of one side each are put into the 1st and 2nd delay circuits 5 and 6 having the same delay time to obtain the delayed signals (e) and (f). Then the shaping reference signal (a) and the delayed signal (f) to be measured are set to one pair; and the shaping signal (c) to be measured and the delayed reference signal (e) are set to the other pair. These pairs are then put into the 1st and 2nd set/reset flip-flop circuits 7 and 8, and the outputs (g) and (h) signals of the circuits 7 and 8 each are put into the integral networks 9 and 10 to be integrated. A subtraction is given to each value of integration through the subtractor circuit 11, and thus the output showing the phase difference is obtained by the value of the above subtraction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17102079A JPS5694828A (en) | 1979-12-28 | 1979-12-28 | Phase difference detecting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17102079A JPS5694828A (en) | 1979-12-28 | 1979-12-28 | Phase difference detecting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5694828A true JPS5694828A (en) | 1981-07-31 |
| JPH0122774B2 JPH0122774B2 (en) | 1989-04-27 |
Family
ID=15915594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17102079A Granted JPS5694828A (en) | 1979-12-28 | 1979-12-28 | Phase difference detecting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5694828A (en) |
-
1979
- 1979-12-28 JP JP17102079A patent/JPS5694828A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0122774B2 (en) | 1989-04-27 |
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